zhoujie
fee2e96eaa
- 新增VSCode编辑器配置，启用保存时自动格式化 - 新增DMA2_Stream5和USART1中断处理函数，优化SPI传输性能 - 移除TIM1相关配置和性能监控模块，简化系统架构 - 优化GPIO配置，将ADC_SYNC和PA8引脚合并配置 - 简化系统监控模块，仅保留采样计数和数据溢出统计 - 优化SPI配置，使用16位数据宽度并提高DMA优先级 - 提高USART波特率（USART1:2Mbps, USART3:921600bps） - 优化LTC2508驱动，增加初始化状态检查和缓冲区大小 - 修正数据存储模块，使用校正数据包而非校正结果结构体 - 优化RS485驱动，使用中断传输并添加传输完成回调 - 更新IOC配置文件，移除TIM1并调整中断优先级配置 - 新增系统监控简化说明文档，详细记录架构变更
75 lines
2.4 KiB
C
75 lines
2.4 KiB
C
/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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* @file dma.c
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* @brief This file provides code for the configuration
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* of all the requested memory to memory DMA transfers.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2026 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* USER CODE END Header */
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/* Includes ------------------------------------------------------------------*/
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#include "dma.h"
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/* USER CODE BEGIN 0 */
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/* USER CODE END 0 */
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/*----------------------------------------------------------------------------*/
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/* Configure DMA */
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/*----------------------------------------------------------------------------*/
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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/**
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* Enable DMA controller clock
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*/
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void MX_DMA_Init(void)
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{
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/* DMA controller clock enable */
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__HAL_RCC_DMA2_CLK_ENABLE();
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__HAL_RCC_DMA1_CLK_ENABLE();
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/* DMA interrupt init */
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/* DMA1_Stream0_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
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/* DMA1_Stream3_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
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/* DMA2_Stream0_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
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/* DMA2_Stream3_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 10, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
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/* DMA2_Stream5_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn);
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/* DMA2_Stream6_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 10, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn);
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/* DMA2_Stream7_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 12, 0);
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HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn);
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}
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/* USER CODE BEGIN 2 */
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/* USER CODE END 2 */
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