init
This commit is contained in:
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*.o
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*.d
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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<storageModule moduleId="org.eclipse.cdt.core.settings">
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<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
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<externalSettings/>
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<extensions>
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<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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</extensions>
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</storageModule>
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<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release">
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<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.1244756189" name="GNU RISC-V Cross Assembler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler">
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|
||||||
|
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
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|
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|
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|
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|
<listOptionValue builtIn="false" value=""../LD""/>
|
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|
</option>
|
||||||
|
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile.1751226764" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile" valueType="stringList">
|
||||||
|
<listOptionValue builtIn="false" value="Link.ld"/>
|
||||||
|
</option>
|
||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart.642896175" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano.1540675679" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano" value="true" valueType="boolean"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1292785366" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver"/>
|
||||||
|
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1801165667" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash">
|
||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice.1490695600" name="Output file format (-O)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice.ihex" valueType="enumerated"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1356766765" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting">
|
||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.2052761852" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders.439659821" name="Display all headers (--all-headers|-x)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle.67111865" name="Demangle names (--demangle|-C)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers.1549373929" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide.1298918921" name="Wide lines (--wide|-w)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||||
|
</tool>
|
||||||
|
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.712424314" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
|
||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1404031980" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
|
||||||
|
</tool>
|
||||||
|
</toolChain>
|
||||||
|
</folderInfo>
|
||||||
|
<sourceEntries>
|
||||||
|
<entry excluding="NetLib|ETH_driver|Startup|Peripheral|Ld|Debug|Core" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
|
||||||
|
<entry excluding="eth_driver_10M.c|eth_driver_RMII.c|eth_driver_CH32V317.c|eth_driver_MII.c|libwchnet_float.a" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="NetLib"/>
|
||||||
|
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
|
||||||
|
<entry excluding="startup_ch32v30x.S|startup_ch32v30x_D8.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
|
||||||
|
</sourceEntries>
|
||||||
|
</configuration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||||
|
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
|
||||||
|
</cconfiguration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||||
|
<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="scannerConfiguration">
|
||||||
|
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
|
||||||
|
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
</scannerConfigBuildInfo>
|
||||||
|
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
|
||||||
|
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
</scannerConfigBuildInfo>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
|
||||||
|
</cproject>
|
||||||
@@ -0,0 +1,53 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<projectDescription>
|
||||||
|
<name>TCPClient</name>
|
||||||
|
<comment></comment>
|
||||||
|
<projects>
|
||||||
|
</projects>
|
||||||
|
<buildSpec>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||||
|
<triggers>clean,full,incremental,</triggers>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||||
|
<triggers>full,incremental,</triggers>
|
||||||
|
<arguments>
|
||||||
|
</arguments>
|
||||||
|
</buildCommand>
|
||||||
|
</buildSpec>
|
||||||
|
<natures>
|
||||||
|
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||||
|
</natures>
|
||||||
|
<linkedResources>
|
||||||
|
<link>
|
||||||
|
<name>Core</name>
|
||||||
|
<type>2</type>
|
||||||
|
<locationURI>PARENT-2-PROJECT_LOC/SRC/Core</locationURI>
|
||||||
|
</link>
|
||||||
|
<link>
|
||||||
|
<name>Debug</name>
|
||||||
|
<type>2</type>
|
||||||
|
<locationURI>PARENT-2-PROJECT_LOC/SRC/Debug</locationURI>
|
||||||
|
</link>
|
||||||
|
<link>
|
||||||
|
<name>NetLib</name>
|
||||||
|
<type>2</type>
|
||||||
|
<locationURI>PARENT-1-PROJECT_LOC/NetLib</locationURI>
|
||||||
|
</link>
|
||||||
|
<link>
|
||||||
|
<name>Peripheral</name>
|
||||||
|
<type>2</type>
|
||||||
|
<locationURI>PARENT-2-PROJECT_LOC/SRC/Peripheral</locationURI>
|
||||||
|
</link>
|
||||||
|
<link>
|
||||||
|
<name>Startup</name>
|
||||||
|
<type>2</type>
|
||||||
|
<locationURI>PARENT-2-PROJECT_LOC/SRC/Startup</locationURI>
|
||||||
|
</link>
|
||||||
|
</linkedResources>
|
||||||
|
</projectDescription>
|
||||||
@@ -0,0 +1,14 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<project>
|
||||||
|
<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj">
|
||||||
|
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||||
|
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||||
|
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||||
|
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||||
|
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="1624694798133818882" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||||
|
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||||
|
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||||
|
</provider>
|
||||||
|
</extension>
|
||||||
|
</configuration>
|
||||||
|
</project>
|
||||||
@@ -0,0 +1,3 @@
|
|||||||
|
eclipse.preferences.version=1
|
||||||
|
encoding//User/ch32v30x_it.c=UTF-8
|
||||||
|
encoding//User/main.c=UTF-8
|
||||||
@@ -0,0 +1,2 @@
|
|||||||
|
eclipse.preferences.version=1
|
||||||
|
org.eclipse.ltk.core.refactoring.enable.project.refactoring.history=false
|
||||||
@@ -0,0 +1,19 @@
|
|||||||
|
Toolchain=RISC-V
|
||||||
|
Series=CH32V307
|
||||||
|
RTOS=NoneOS
|
||||||
|
PeripheralVersion=======1.4
|
||||||
|
Description=======ROM(byte): 256K, SRAM(byte): 64K, CHIP PINS: 64, GPIO PORTS: 51.\nWCH CH32V3 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
|
||||||
|
Address=0x08000000
|
||||||
|
Target Path=obj\TCPClient.hex
|
||||||
|
CLKSpeed=1
|
||||||
|
DebugInterfaceMode=-1
|
||||||
|
Erase All=true
|
||||||
|
Program=true
|
||||||
|
Verify=true
|
||||||
|
Reset=true
|
||||||
|
SDIPrintf=false
|
||||||
|
|
||||||
|
Vendor=WCH
|
||||||
|
MCU=CH32V307RCT6
|
||||||
|
Mcu Type=CH32V30x
|
||||||
|
Link=WCH-Link
|
||||||
@@ -0,0 +1,392 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : core_riscv.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.1
|
||||||
|
* Date : 2023/11/11
|
||||||
|
* Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32V30x
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/* define compiler specific symbols */
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||||
|
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_FFLAGS
|
||||||
|
*
|
||||||
|
* @brief Return the Floating-Point Accrued Exceptions
|
||||||
|
*
|
||||||
|
* @return fflags value
|
||||||
|
*/
|
||||||
|
uint32_t __get_FFLAGS(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "fflags" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_FFLAGS
|
||||||
|
*
|
||||||
|
* @brief Set the Floating-Point Accrued Exceptions
|
||||||
|
*
|
||||||
|
* @param value - set FFLAGS value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_FFLAGS(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw fflags, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_FRM
|
||||||
|
*
|
||||||
|
* @brief Return the Floating-Point Dynamic Rounding Mode
|
||||||
|
*
|
||||||
|
* @return frm value
|
||||||
|
*/
|
||||||
|
uint32_t __get_FRM(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "frm" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_FRM
|
||||||
|
*
|
||||||
|
* @brief Set the Floating-Point Dynamic Rounding Mode
|
||||||
|
*
|
||||||
|
* @param value - set frm value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_FRM(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw frm, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_FCSR
|
||||||
|
*
|
||||||
|
* @brief Return the Floating-Point Control and Status Register
|
||||||
|
*
|
||||||
|
* @return fcsr value
|
||||||
|
*/
|
||||||
|
uint32_t __get_FCSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "fcsr" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_FCSR
|
||||||
|
*
|
||||||
|
* @brief Set the Floating-Point Dynamic Rounding Mode
|
||||||
|
*
|
||||||
|
* @param value - set fcsr value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_FCSR(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw fcsr, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MSTATUS
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Status Register
|
||||||
|
*
|
||||||
|
* @return mstatus value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MSTATUS(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MSTATUS
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Status Register
|
||||||
|
*
|
||||||
|
* @param value - set mstatus value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_MSTATUS(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mstatus, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MISA
|
||||||
|
*
|
||||||
|
* @brief Return the Machine ISA Register
|
||||||
|
*
|
||||||
|
* @return misa value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MISA(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "misa" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MISA
|
||||||
|
*
|
||||||
|
* @brief Set the Machine ISA Register
|
||||||
|
*
|
||||||
|
* @param value - set misa value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_MISA(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw misa, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MTVEC
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Trap-Vector Base-Address Register
|
||||||
|
*
|
||||||
|
* @return mtvec value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MTVEC(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MTVEC
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Trap-Vector Base-Address Register
|
||||||
|
*
|
||||||
|
* @param value - set mtvec value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_MTVEC(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mtvec, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MSCRATCH
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Seratch Register
|
||||||
|
*
|
||||||
|
* @return mscratch value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MSCRATCH(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MSCRATCH
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Seratch Register
|
||||||
|
*
|
||||||
|
* @param value - set mscratch value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_MSCRATCH(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mscratch, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MEPC
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Exception Program Register
|
||||||
|
*
|
||||||
|
* @return mepc value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MEPC(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MEPC
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Exception Program Register
|
||||||
|
*
|
||||||
|
* @return mepc value
|
||||||
|
*/
|
||||||
|
void __set_MEPC(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mepc, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MCAUSE
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Cause Register
|
||||||
|
*
|
||||||
|
* @return mcause value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MCAUSE(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MEPC
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Cause Register
|
||||||
|
*
|
||||||
|
* @return mcause value
|
||||||
|
*/
|
||||||
|
void __set_MCAUSE(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mcause, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MTVAL
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Trap Value Register
|
||||||
|
*
|
||||||
|
* @return mtval value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MTVAL(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MTVAL
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Trap Value Register
|
||||||
|
*
|
||||||
|
* @return mtval value
|
||||||
|
*/
|
||||||
|
void __set_MTVAL(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mtval, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MVENDORID
|
||||||
|
*
|
||||||
|
* @brief Return Vendor ID Register
|
||||||
|
*
|
||||||
|
* @return mvendorid value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MVENDORID(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MARCHID
|
||||||
|
*
|
||||||
|
* @brief Return Machine Architecture ID Register
|
||||||
|
*
|
||||||
|
* @return marchid value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MARCHID(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MIMPID
|
||||||
|
*
|
||||||
|
* @brief Return Machine Implementation ID Register
|
||||||
|
*
|
||||||
|
* @return mimpid value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MIMPID(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MHARTID
|
||||||
|
*
|
||||||
|
* @brief Return Hart ID Register
|
||||||
|
*
|
||||||
|
* @return mhartid value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MHARTID(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_SP
|
||||||
|
*
|
||||||
|
* @brief Return SP Register
|
||||||
|
*
|
||||||
|
* @return SP value
|
||||||
|
*/
|
||||||
|
uint32_t __get_SP(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "mv %0," "sp" : "=r"(result) : );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
@@ -0,0 +1,599 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : core_riscv.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.2
|
||||||
|
* Date : 2025/03/06
|
||||||
|
* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32V30x
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CORE_RISCV_H__
|
||||||
|
#define __CORE_RISCV_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /* defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /* defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /* defines 'write only' permissions */
|
||||||
|
#define __IO volatile /* defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/* Standard Peripheral Library old types (maintained for legacy purpose) */
|
||||||
|
typedef __I uint64_t vuc64; /* Read Only */
|
||||||
|
typedef __I uint32_t vuc32; /* Read Only */
|
||||||
|
typedef __I uint16_t vuc16; /* Read Only */
|
||||||
|
typedef __I uint8_t vuc8; /* Read Only */
|
||||||
|
|
||||||
|
typedef const uint64_t uc64; /* Read Only */
|
||||||
|
typedef const uint32_t uc32; /* Read Only */
|
||||||
|
typedef const uint16_t uc16; /* Read Only */
|
||||||
|
typedef const uint8_t uc8; /* Read Only */
|
||||||
|
|
||||||
|
typedef __I int64_t vsc64; /* Read Only */
|
||||||
|
typedef __I int32_t vsc32; /* Read Only */
|
||||||
|
typedef __I int16_t vsc16; /* Read Only */
|
||||||
|
typedef __I int8_t vsc8; /* Read Only */
|
||||||
|
|
||||||
|
typedef const int64_t sc64; /* Read Only */
|
||||||
|
typedef const int32_t sc32; /* Read Only */
|
||||||
|
typedef const int16_t sc16; /* Read Only */
|
||||||
|
typedef const int8_t sc8; /* Read Only */
|
||||||
|
|
||||||
|
typedef __IO uint64_t vu64;
|
||||||
|
typedef __IO uint32_t vu32;
|
||||||
|
typedef __IO uint16_t vu16;
|
||||||
|
typedef __IO uint8_t vu8;
|
||||||
|
|
||||||
|
typedef uint64_t u64;
|
||||||
|
typedef uint32_t u32;
|
||||||
|
typedef uint16_t u16;
|
||||||
|
typedef uint8_t u8;
|
||||||
|
|
||||||
|
typedef __IO int64_t vs64;
|
||||||
|
typedef __IO int32_t vs32;
|
||||||
|
typedef __IO int16_t vs16;
|
||||||
|
typedef __IO int8_t vs8;
|
||||||
|
|
||||||
|
typedef int64_t s64;
|
||||||
|
typedef int32_t s32;
|
||||||
|
typedef int16_t s16;
|
||||||
|
typedef int8_t s8;
|
||||||
|
|
||||||
|
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
|
||||||
|
|
||||||
|
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||||
|
|
||||||
|
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||||
|
|
||||||
|
#define RV_STATIC_INLINE static inline
|
||||||
|
|
||||||
|
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
|
||||||
|
typedef struct{
|
||||||
|
__I uint32_t ISR[8];
|
||||||
|
__I uint32_t IPR[8];
|
||||||
|
__IO uint32_t ITHRESDR;
|
||||||
|
__IO uint32_t RESERVED;
|
||||||
|
__IO uint32_t CFGR;
|
||||||
|
__I uint32_t GISR;
|
||||||
|
__IO uint8_t VTFIDR[4];
|
||||||
|
uint8_t RESERVED0[12];
|
||||||
|
__IO uint32_t VTFADDR[4];
|
||||||
|
uint8_t RESERVED1[0x90];
|
||||||
|
__O uint32_t IENR[8];
|
||||||
|
uint8_t RESERVED2[0x60];
|
||||||
|
__O uint32_t IRER[8];
|
||||||
|
uint8_t RESERVED3[0x60];
|
||||||
|
__O uint32_t IPSR[8];
|
||||||
|
uint8_t RESERVED4[0x60];
|
||||||
|
__O uint32_t IPRR[8];
|
||||||
|
uint8_t RESERVED5[0x60];
|
||||||
|
__IO uint32_t IACTR[8];
|
||||||
|
uint8_t RESERVED6[0xE0];
|
||||||
|
__IO uint8_t IPRIOR[256];
|
||||||
|
uint8_t RESERVED7[0x810];
|
||||||
|
__IO uint32_t SCTLR;
|
||||||
|
}PFIC_Type;
|
||||||
|
|
||||||
|
/* memory mapped structure for SysTick */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint32_t CTLR;
|
||||||
|
__IO uint32_t SR;
|
||||||
|
__IO uint64_t CNT;
|
||||||
|
__IO uint64_t CMP;
|
||||||
|
}SysTick_Type;
|
||||||
|
|
||||||
|
|
||||||
|
#define PFIC ((PFIC_Type *) 0xE000E000 )
|
||||||
|
#define NVIC PFIC
|
||||||
|
#define NVIC_KEY1 ((uint32_t)0xFA050000)
|
||||||
|
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||||
|
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
|
||||||
|
|
||||||
|
#define SysTick ((SysTick_Type *) 0xE000F000)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __enable_irq
|
||||||
|
*
|
||||||
|
* @brief Enable Global Interrupt
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
|
||||||
|
{
|
||||||
|
__asm volatile ("csrs 0x800, %0" : : "r" (0x88) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __disable_irq
|
||||||
|
*
|
||||||
|
* @brief Disable Global Interrupt
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
|
||||||
|
{
|
||||||
|
__asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
|
||||||
|
__asm volatile ("fence.i");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __NOP
|
||||||
|
*
|
||||||
|
* @brief nop
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
|
||||||
|
{
|
||||||
|
__asm volatile ("nop");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_EnableIRQ
|
||||||
|
*
|
||||||
|
* @brief Enable Interrupt
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_DisableIRQ
|
||||||
|
*
|
||||||
|
* @brief Disable Interrupt
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
__asm volatile ("fence.i");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_GetStatusIRQ
|
||||||
|
*
|
||||||
|
* @brief Get Interrupt Enable State
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return 1 - Interrupt Enable
|
||||||
|
* 0 - Interrupt Disable
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_GetPendingIRQ
|
||||||
|
*
|
||||||
|
* @brief Get Interrupt Pending State
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return 1 - Interrupt Pending Enable
|
||||||
|
* 0 - Interrupt Pending Disable
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_SetPendingIRQ
|
||||||
|
*
|
||||||
|
* @brief Set Interrupt Pending
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_ClearPendingIRQ
|
||||||
|
*
|
||||||
|
* @brief Clear Interrupt Pending
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_GetActive
|
||||||
|
*
|
||||||
|
* @brief Get Interrupt Active State
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return 1 - Interrupt Active
|
||||||
|
* 0 - Interrupt No Active
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_SetPriority
|
||||||
|
*
|
||||||
|
* @brief Set Interrupt Priority
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3)
|
||||||
|
* priority - bit[7:5] - Preemption Priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2)
|
||||||
|
* priority - bit[7:6] - Preemption Priority
|
||||||
|
* bit[5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1)
|
||||||
|
* priority - bit[7] - Preemption Priority
|
||||||
|
* bit[6:5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||||
|
* priority - bit[7:5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
|
||||||
|
{
|
||||||
|
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __WFI
|
||||||
|
*
|
||||||
|
* @brief Wait for Interrupt
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
|
||||||
|
{
|
||||||
|
NVIC->SCTLR &= ~(1<<3); // wfi
|
||||||
|
asm volatile ("wfi");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn _SEV
|
||||||
|
*
|
||||||
|
* @brief Set Event
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
|
||||||
|
{
|
||||||
|
uint32_t t;
|
||||||
|
|
||||||
|
t = NVIC->SCTLR;
|
||||||
|
NVIC->SCTLR |= (1<<3)|(1<<5);
|
||||||
|
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn _WFE
|
||||||
|
*
|
||||||
|
* @brief Wait for Events
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
|
||||||
|
{
|
||||||
|
NVIC->SCTLR |= (1<<3);
|
||||||
|
asm volatile ("wfi");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __WFE
|
||||||
|
*
|
||||||
|
* @brief Wait for Events
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
|
||||||
|
{
|
||||||
|
_SEV();
|
||||||
|
_WFE();
|
||||||
|
_WFE();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SetVTFIRQ
|
||||||
|
*
|
||||||
|
* @brief Set VTF Interrupt
|
||||||
|
*
|
||||||
|
* @param add - VTF interrupt service function base address.
|
||||||
|
* IRQn -Interrupt Numbers
|
||||||
|
* num - VTF Interrupt Numbers
|
||||||
|
* NewState - DISABLE or ENABLE
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(num > 3) return ;
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
NVIC->VTFIDR[num] = IRQn;
|
||||||
|
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
NVIC->VTFIDR[num] = IRQn;
|
||||||
|
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_SystemReset
|
||||||
|
*
|
||||||
|
* @brief Initiate a system reset request
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
NVIC->CFGR = NVIC_KEY3|(1<<7);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOADD_W
|
||||||
|
*
|
||||||
|
* @brief Atomic Add with 32bit value
|
||||||
|
* Atomically ADD 32bit value with value in memory using amoadd.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be ADDed
|
||||||
|
*
|
||||||
|
* @return return memory value + add value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amoadd.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOAND_W
|
||||||
|
*
|
||||||
|
* @brief Atomic And with 32bit value
|
||||||
|
* Atomically AND 32bit value with value in memory using amoand.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be ANDed
|
||||||
|
*
|
||||||
|
* @return return memory value & and value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amoand.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOMAX_W
|
||||||
|
*
|
||||||
|
* @brief Atomic signed MAX with 32bit value
|
||||||
|
* Atomically signed max compare 32bit value with value in memory using amomax.d.
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be compared
|
||||||
|
*
|
||||||
|
* @return return the bigger value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amomax.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOMAXU_W
|
||||||
|
*
|
||||||
|
* @brief Atomic unsigned MAX with 32bit value
|
||||||
|
* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be compared
|
||||||
|
*
|
||||||
|
* @return return the bigger value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amomaxu.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOMIN_W
|
||||||
|
*
|
||||||
|
* @brief Atomic signed MIN with 32bit value
|
||||||
|
* Atomically signed min compare 32bit value with value in memory using amomin.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be compared
|
||||||
|
*
|
||||||
|
* @return return the smaller value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amomin.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOMINU_W
|
||||||
|
*
|
||||||
|
* @brief Atomic unsigned MIN with 32bit value
|
||||||
|
* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be compared
|
||||||
|
*
|
||||||
|
* @return return the smaller value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amominu.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOOR_W
|
||||||
|
*
|
||||||
|
* @brief Atomic OR with 32bit value
|
||||||
|
* Atomically OR 32bit value with value in memory using amoor.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be ORed
|
||||||
|
*
|
||||||
|
* @return return memory value | and value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amoor.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOSWAP_W
|
||||||
|
*
|
||||||
|
* @brief Atomically swap new 32bit value into memory using amoswap.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* newval - New value to be stored into the address
|
||||||
|
*
|
||||||
|
* @return return the original value in memory
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amoswap.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOXOR_W
|
||||||
|
*
|
||||||
|
* @brief Atomic XOR with 32bit value
|
||||||
|
* Atomically XOR 32bit value with value in memory using amoxor.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be XORed
|
||||||
|
*
|
||||||
|
* @return return memory value ^ and value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amoxor.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Core_Exported_Functions */
|
||||||
|
extern uint32_t __get_FFLAGS(void);
|
||||||
|
extern void __set_FFLAGS(uint32_t value);
|
||||||
|
extern uint32_t __get_FRM(void);
|
||||||
|
extern void __set_FRM(uint32_t value);
|
||||||
|
extern uint32_t __get_FCSR(void);
|
||||||
|
extern void __set_FCSR(uint32_t value);
|
||||||
|
extern uint32_t __get_MSTATUS(void);
|
||||||
|
extern void __set_MSTATUS(uint32_t value);
|
||||||
|
extern uint32_t __get_MISA(void);
|
||||||
|
extern void __set_MISA(uint32_t value);
|
||||||
|
extern uint32_t __get_MTVEC(void);
|
||||||
|
extern void __set_MTVEC(uint32_t value);
|
||||||
|
extern uint32_t __get_MSCRATCH(void);
|
||||||
|
extern void __set_MSCRATCH(uint32_t value);
|
||||||
|
extern uint32_t __get_MEPC(void);
|
||||||
|
extern void __set_MEPC(uint32_t value);
|
||||||
|
extern uint32_t __get_MCAUSE(void);
|
||||||
|
extern void __set_MCAUSE(uint32_t value);
|
||||||
|
extern uint32_t __get_MTVAL(void);
|
||||||
|
extern void __set_MTVAL(uint32_t value);
|
||||||
|
extern uint32_t __get_MVENDORID(void);
|
||||||
|
extern uint32_t __get_MARCHID(void);
|
||||||
|
extern uint32_t __get_MIMPID(void);
|
||||||
|
extern uint32_t __get_MHARTID(void);
|
||||||
|
extern uint32_t __get_SP(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,327 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : debug.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for UART
|
||||||
|
* Printf , Delay functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "debug.h"
|
||||||
|
|
||||||
|
static uint8_t p_us = 0;
|
||||||
|
static uint16_t p_ms = 0;
|
||||||
|
|
||||||
|
#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380)
|
||||||
|
#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn Delay_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes Delay Funcation.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void Delay_Init(void)
|
||||||
|
{
|
||||||
|
p_us = SystemCoreClock / 8000000;
|
||||||
|
p_ms = (uint16_t)p_us * 1000;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn Delay_Us
|
||||||
|
*
|
||||||
|
* @brief Microsecond Delay Time.
|
||||||
|
*
|
||||||
|
* @param n - Microsecond number.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void Delay_Us(uint32_t n)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
SysTick->SR &= ~(1 << 0);
|
||||||
|
i = (uint32_t)n * p_us;
|
||||||
|
|
||||||
|
SysTick->CMP = i;
|
||||||
|
SysTick->CTLR |= (1 << 4);
|
||||||
|
SysTick->CTLR |= (1 << 5) | (1 << 0);
|
||||||
|
|
||||||
|
while((SysTick->SR & (1 << 0)) != (1 << 0))
|
||||||
|
;
|
||||||
|
SysTick->CTLR &= ~(1 << 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn Delay_Ms
|
||||||
|
*
|
||||||
|
* @brief Millisecond Delay Time.
|
||||||
|
*
|
||||||
|
* @param n - Millisecond number.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void Delay_Ms(uint32_t n)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
SysTick->SR &= ~(1 << 0);
|
||||||
|
i = (uint32_t)n * p_ms;
|
||||||
|
|
||||||
|
SysTick->CMP = i;
|
||||||
|
SysTick->CTLR |= (1 << 4);
|
||||||
|
SysTick->CTLR |= (1 << 5) | (1 << 0);
|
||||||
|
|
||||||
|
while((SysTick->SR & (1 << 0)) != (1 << 0))
|
||||||
|
;
|
||||||
|
SysTick->CTLR &= ~(1 << 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_Printf_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the USARTx peripheral.
|
||||||
|
*
|
||||||
|
* @param baudrate - USART communication baud rate.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USART_Printf_Init(uint32_t baudrate)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
USART_InitTypeDef USART_InitStructure;
|
||||||
|
|
||||||
|
#if(DEBUG == DEBUG_UART1)
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
#elif(DEBUG == DEBUG_UART2)
|
||||||
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
#elif(DEBUG == DEBUG_UART3)
|
||||||
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
USART_InitStructure.USART_BaudRate = baudrate;
|
||||||
|
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||||
|
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||||
|
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||||
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||||
|
USART_InitStructure.USART_Mode = USART_Mode_Tx;
|
||||||
|
|
||||||
|
#if(DEBUG == DEBUG_UART1)
|
||||||
|
USART_Init(USART1, &USART_InitStructure);
|
||||||
|
USART_Cmd(USART1, ENABLE);
|
||||||
|
|
||||||
|
#elif(DEBUG == DEBUG_UART2)
|
||||||
|
USART_Init(USART2, &USART_InitStructure);
|
||||||
|
USART_Cmd(USART2, ENABLE);
|
||||||
|
|
||||||
|
#elif(DEBUG == DEBUG_UART3)
|
||||||
|
USART_Init(USART3, &USART_InitStructure);
|
||||||
|
USART_Cmd(USART3, ENABLE);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDI_Printf_Enable
|
||||||
|
*
|
||||||
|
* @brief Initializes the SDI printf Function.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void SDI_Printf_Enable(void)
|
||||||
|
{
|
||||||
|
*(DEBUG_DATA0_ADDRESS) = 0;
|
||||||
|
Delay_Init();
|
||||||
|
Delay_Ms(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn _write
|
||||||
|
*
|
||||||
|
* @brief Support Printf Function
|
||||||
|
*
|
||||||
|
* @param *buf - UART send Data.
|
||||||
|
* size - Data length
|
||||||
|
*
|
||||||
|
* @return size: Data length
|
||||||
|
*/
|
||||||
|
__attribute__((used)) int _write(int fd, char *buf, int size)
|
||||||
|
{
|
||||||
|
int i = 0;
|
||||||
|
|
||||||
|
#if (SDI_PRINT == SDI_PR_OPEN)
|
||||||
|
int writeSize = size;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
|
||||||
|
/**
|
||||||
|
* data0 data1 8 bytes
|
||||||
|
* data0 The lowest byte storage length, the maximum is 7
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
while( (*(DEBUG_DATA0_ADDRESS) != 0u))
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
if(writeSize>7)
|
||||||
|
{
|
||||||
|
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
|
||||||
|
*(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
|
||||||
|
|
||||||
|
i += 7;
|
||||||
|
writeSize -= 7;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
|
||||||
|
*(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
|
||||||
|
|
||||||
|
writeSize = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
} while (writeSize);
|
||||||
|
|
||||||
|
|
||||||
|
#else
|
||||||
|
for(i = 0; i < size; i++)
|
||||||
|
{
|
||||||
|
#if(DEBUG == DEBUG_UART1)
|
||||||
|
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
|
||||||
|
USART_SendData(USART1, *buf++);
|
||||||
|
#elif(DEBUG == DEBUG_UART2)
|
||||||
|
while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
|
||||||
|
USART_SendData(USART2, *buf++);
|
||||||
|
#elif(DEBUG == DEBUG_UART3)
|
||||||
|
while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
|
||||||
|
USART_SendData(USART3, *buf++);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
return size;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn _sbrk
|
||||||
|
*
|
||||||
|
* @brief Change the spatial position of data segment.
|
||||||
|
*
|
||||||
|
* @return size: Data length
|
||||||
|
*/
|
||||||
|
__attribute__((used)) void *_sbrk(ptrdiff_t incr)
|
||||||
|
{
|
||||||
|
extern char _end[];
|
||||||
|
extern char _heap_end[];
|
||||||
|
static char *curbrk = _end;
|
||||||
|
|
||||||
|
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
|
||||||
|
return NULL - 1;
|
||||||
|
|
||||||
|
curbrk += incr;
|
||||||
|
return curbrk - incr;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief 初始化LED相关IO口, 并使能时钟
|
||||||
|
* @param 无
|
||||||
|
* @retval 无
|
||||||
|
*/
|
||||||
|
void led_init(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef gpio_init_struct;
|
||||||
|
LED0_GPIO_CLK_ENABLE(); /* LED0时钟使能 */
|
||||||
|
LED1_GPIO_CLK_ENABLE(); /* LED1时钟使能 */
|
||||||
|
LED2_GPIO_CLK_ENABLE(); /* LED2时钟使能 */
|
||||||
|
INPUT_GPIO_CLK_ENABLE(); /* 输入引脚时钟使能 */
|
||||||
|
OUTPUT1_GPIO_CLK_ENABLE(); /* 输出1引脚时钟使能 */
|
||||||
|
OUTPUT2_GPIO_CLK_ENABLE(); /* 输出2引脚时钟使能 */
|
||||||
|
|
||||||
|
gpio_init_struct.GPIO_Pin = LED0_GPIO_PIN; /* LED0引脚 */
|
||||||
|
gpio_init_struct.GPIO_Mode = GPIO_Mode_Out_PP; /* 推挽输出 */
|
||||||
|
gpio_init_struct.GPIO_Speed = GPIO_Speed_50MHz; /* 高速 */
|
||||||
|
GPIO_Init(LED0_GPIO_PORT, &gpio_init_struct); /* 初始化LED0引脚 */
|
||||||
|
|
||||||
|
gpio_init_struct.GPIO_Pin = LED1_GPIO_PIN; /* LED1引脚 */
|
||||||
|
GPIO_Init(LED1_GPIO_PORT, &gpio_init_struct); /* 初始化LED1引脚 */
|
||||||
|
|
||||||
|
gpio_init_struct.GPIO_Pin = LED2_GPIO_PIN; /* LED2引脚 */
|
||||||
|
GPIO_Init(LED2_GPIO_PORT, &gpio_init_struct); /* 初始化LED2引脚 */
|
||||||
|
|
||||||
|
gpio_init_struct.GPIO_Pin = INPUT_GPIO_PIN; /* INPUT引脚 */
|
||||||
|
gpio_init_struct.GPIO_Mode = GPIO_Mode_IPU; /* 上拉输入 */
|
||||||
|
GPIO_Init(INPUT_GPIO_PORT, &gpio_init_struct); /* 初始化INPUT引脚 */
|
||||||
|
|
||||||
|
gpio_init_struct.GPIO_Pin = OUTPUT1_GPIO_PIN | OUTPUT2_GPIO_PIN; /* OUTPUT引脚 */
|
||||||
|
gpio_init_struct.GPIO_Mode = GPIO_Mode_Out_PP; /* 推挽输出 */
|
||||||
|
GPIO_Init(OUTPUT1_GPIO_PORT, &gpio_init_struct); /* 初始化OUTPUT引脚 */
|
||||||
|
|
||||||
|
|
||||||
|
LED0(1); /* 关闭 LED0 */
|
||||||
|
LED1(1); /* 关闭 LED1 */
|
||||||
|
LED2(1); /* 关闭 LED2 */
|
||||||
|
OUTPUT1(0); /* 拉低DO1 */
|
||||||
|
OUTPUT2(0); /* 拉低DO2 */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void check_input(void)
|
||||||
|
{
|
||||||
|
if (GPIO_ReadInputDataBit(INPUT_GPIO_PORT, INPUT_GPIO_PIN) == Bit_RESET) {
|
||||||
|
LED0(0);
|
||||||
|
} else {
|
||||||
|
LED0(1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
void set_outpot(uint8_t pd8_state, uint8_t pd9_state)
|
||||||
|
{
|
||||||
|
if(pd8_state)
|
||||||
|
GPIO_SetBits(OUTPUT1_GPIO_PORT, OUTPUT1_GPIO_PIN); /* PD8拉高 */
|
||||||
|
else
|
||||||
|
GPIO_ResetBits(OUTPUT1_GPIO_PORT, OUTPUT1_GPIO_PIN); /* PD8拉低 */
|
||||||
|
|
||||||
|
if(pd9_state)
|
||||||
|
GPIO_SetBits(OUTPUT2_GPIO_PORT, OUTPUT2_GPIO_PIN); /* PD9拉高 */
|
||||||
|
else
|
||||||
|
GPIO_ResetBits(OUTPUT2_GPIO_PORT, OUTPUT2_GPIO_PIN); /* PD9拉低 */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,128 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : debug.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for UART
|
||||||
|
* Printf , Delay functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __DEBUG_H
|
||||||
|
#define __DEBUG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "stdio.h"
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* UART Printf Definition */
|
||||||
|
#define DEBUG_UART1 1
|
||||||
|
#define DEBUG_UART2 2
|
||||||
|
#define DEBUG_UART3 3
|
||||||
|
|
||||||
|
/* DEBUG UATR Definition */
|
||||||
|
#ifndef DEBUG
|
||||||
|
#define DEBUG DEBUG_UART3
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* SDI Printf Definition */
|
||||||
|
#define SDI_PR_CLOSE 0
|
||||||
|
#define SDI_PR_OPEN 1
|
||||||
|
|
||||||
|
#ifndef SDI_PRINT
|
||||||
|
#define SDI_PRINT SDI_PR_CLOSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* 引脚 定义 */
|
||||||
|
#define LED0_GPIO_PORT GPIOB
|
||||||
|
#define LED0_GPIO_PIN GPIO_Pin_5
|
||||||
|
#define LED0_GPIO_CLK_ENABLE() do{ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); }while(0) /* PB口时钟使能 */
|
||||||
|
|
||||||
|
#define LED1_GPIO_PORT GPIOB
|
||||||
|
#define LED1_GPIO_PIN GPIO_Pin_6
|
||||||
|
#define LED1_GPIO_CLK_ENABLE() do{ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); }while(0) /* PB口时钟使能 */
|
||||||
|
|
||||||
|
#define LED2_GPIO_PORT GPIOB
|
||||||
|
#define LED2_GPIO_PIN GPIO_Pin_7
|
||||||
|
#define LED2_GPIO_CLK_ENABLE() do{ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); }while(0) /* PC口时钟使能 */
|
||||||
|
|
||||||
|
#define INPUT_GPIO_PORT GPIOB
|
||||||
|
#define INPUT_GPIO_PIN GPIO_Pin_14
|
||||||
|
#define INPUT_GPIO_CLK_ENABLE() do{ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); }while(0) /* PA口时钟使能 */
|
||||||
|
|
||||||
|
#define OUTPUT1_GPIO_PORT GPIOD
|
||||||
|
#define OUTPUT1_GPIO_PIN GPIO_Pin_8
|
||||||
|
#define OUTPUT1_GPIO_CLK_ENABLE() do{ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); }while(0) /* PD口时钟使能 */
|
||||||
|
|
||||||
|
#define OUTPUT2_GPIO_PORT GPIOD
|
||||||
|
#define OUTPUT2_GPIO_PIN GPIO_Pin_9
|
||||||
|
#define OUTPUT2_GPIO_CLK_ENABLE() do{ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE); }while(0) /* PD口时钟使能 */
|
||||||
|
|
||||||
|
/******************************************************************************************/
|
||||||
|
|
||||||
|
/* LED端口定义 */
|
||||||
|
#define LED0(x) do{ x ? \
|
||||||
|
GPIO_SetBits(LED0_GPIO_PORT,LED0_GPIO_PIN): \
|
||||||
|
GPIO_ResetBits(LED0_GPIO_PORT,LED0_GPIO_PIN); \
|
||||||
|
}while(0) /* LED0 = BLUE */
|
||||||
|
|
||||||
|
#define LED1(x) do{ x ? \
|
||||||
|
GPIO_SetBits(LED1_GPIO_PORT,LED1_GPIO_PIN): \
|
||||||
|
GPIO_ResetBits(LED1_GPIO_PORT,LED1_GPIO_PIN); \
|
||||||
|
}while(0) /* LED1 = YELLOW */
|
||||||
|
|
||||||
|
#define LED2(x) do{ x ? \
|
||||||
|
GPIO_SetBits(LED2_GPIO_PORT,LED2_GPIO_PIN): \
|
||||||
|
GPIO_ResetBits(LED2_GPIO_PORT,LED2_GPIO_PIN); \
|
||||||
|
}while(0) /* LED2 = GREEN */
|
||||||
|
|
||||||
|
#define INPUT(x) do{ x ? \
|
||||||
|
GPIO_SetBits(INPUT_GPIO_PORT,INPUT_GPIO_PIN): \
|
||||||
|
GPIO_ResetBits(INPUT_GPIO_PORT,INPUT_GPIO_PIN); \
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
#define OUTPUT1(x) do{ x ? \
|
||||||
|
GPIO_SetBits(OUTPUT1_GPIO_PORT,OUTPUT1_GPIO_PIN): \
|
||||||
|
GPIO_ResetBits(OUTPUT1_GPIO_PORT,OUTPUT1_GPIO_PIN); \
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
#define OUTPUT2(x) do{ x ? \
|
||||||
|
GPIO_SetBits(OUTPUT2_GPIO_PORT,OUTPUT2_GPIO_PIN): \
|
||||||
|
GPIO_ResetBits(OUTPUT2_GPIO_PORT,OUTPUT2_GPIO_PIN); \
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
/* LED取反定义 */
|
||||||
|
#define LED0_TOGGLE() do{ gpio_toggle_pin(LED0_GPIO_PORT, LED0_GPIO_PIN); }while(0) /* 翻转LED0 */
|
||||||
|
#define LED1_TOGGLE() do{ gpio_toggle_pin(LED1_GPIO_PORT, LED1_GPIO_PIN); }while(0) /* 翻转LED1 */
|
||||||
|
#define LED2_TOGGLE() do{ gpio_toggle_pin(LED2_GPIO_PORT, LED2_GPIO_PIN); }while(0) /* 翻转LED2 */
|
||||||
|
|
||||||
|
/******************************************************************************************/
|
||||||
|
|
||||||
|
void led_init(void); /* 初始化LED */
|
||||||
|
|
||||||
|
void check_input(void); /*检查PA8口的输入电平*/
|
||||||
|
|
||||||
|
void set_outpot(uint8_t pd8_state, uint8_t pd9_state); /*设置PD8\PD9输出电平*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void Delay_Init(void);
|
||||||
|
void Delay_Us (uint32_t n);
|
||||||
|
void Delay_Ms (uint32_t n);
|
||||||
|
void USART_Printf_Init(uint32_t baudrate);
|
||||||
|
void SDI_Printf_Enable(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,99 @@
|
|||||||
|
#include "dvp.h"
|
||||||
|
#include "ch32v30x_dvp.h"
|
||||||
|
#include "eth_driver.h"
|
||||||
|
#include "string.h"
|
||||||
|
|
||||||
|
__attribute__((aligned(4))) uint8_t DMA_LineBuf0[BYTES_PER_LINE];
|
||||||
|
__attribute__((aligned(4))) uint8_t DMA_LineBuf1[BYTES_PER_LINE];
|
||||||
|
|
||||||
|
volatile uint8_t Line_Ready_Flag = 0;
|
||||||
|
volatile uint8_t *Ready_Line_Ptr = NULL;
|
||||||
|
volatile uint32_t current_line_idx = 0;
|
||||||
|
static uint32_t frame_count = 0;
|
||||||
|
|
||||||
|
extern u8 socket[];
|
||||||
|
|
||||||
|
void DVP_Init(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||||
|
NVIC_InitTypeDef NVIC_InitStructure = {0};
|
||||||
|
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);
|
||||||
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DVP, ENABLE);
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_9 | GPIO_Pin_10;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_11;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9;
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannel = DVP_IRQn;
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||||
|
NVIC_Init(&NVIC_InitStructure);
|
||||||
|
|
||||||
|
DVP_Cfg(DVP_DMA_Disable, DVP_FLAG_FIFO_RESET_Enable, DVP_RX_RESET_Enable);
|
||||||
|
DVP_Mode(RB_DVP_D8_MOD, Video_Mode);
|
||||||
|
DVP->CR0 &= ~(RB_DVP_P_POLAR | RB_DVP_V_POLAR | RB_DVP_H_POLAR);
|
||||||
|
DVP->DMA_BUF0 = (uint32_t)DMA_LineBuf0;
|
||||||
|
DVP->DMA_BUF1 = (uint32_t)DMA_LineBuf1;
|
||||||
|
DVP->ROW_NUM = 1;
|
||||||
|
DVP->COL_NUM = BYTES_PER_LINE;
|
||||||
|
DVP_INTCfg(ENABLE, RB_DVP_IE_STR_FRM | RB_DVP_IE_ROW_DONE);
|
||||||
|
DVP_Cfg(DVP_DMA_Enable, DVP_FLAG_FIFO_RESET_Disable, DVP_RX_RESET_Disable);
|
||||||
|
DVP->CR0 |= RB_DVP_ENABLE;
|
||||||
|
}
|
||||||
|
|
||||||
|
void DVP_Task(void)
|
||||||
|
{
|
||||||
|
if (!Line_Ready_Flag) return;
|
||||||
|
|
||||||
|
uint8_t *line = (uint8_t *)Ready_Line_Ptr;
|
||||||
|
uint32_t idx = current_line_idx;
|
||||||
|
Line_Ready_Flag = 0;
|
||||||
|
|
||||||
|
/* 仅发送图像行，跳过参数行，且 socket 已连接 */
|
||||||
|
if (idx < SENSOR_HEIGHT && socket[0] != 0xFF)
|
||||||
|
{
|
||||||
|
/* 4字节行头：帧号(2B) + 行号(2B) */
|
||||||
|
uint8_t hdr[4] = {
|
||||||
|
(frame_count >> 8) & 0xFF, frame_count & 0xFF,
|
||||||
|
(idx >> 8) & 0xFF, idx & 0xFF
|
||||||
|
};
|
||||||
|
u32 len = 4;
|
||||||
|
WCHNET_SocketSend(socket[0], hdr, &len);
|
||||||
|
len = BYTES_PER_LINE;
|
||||||
|
WCHNET_SocketSend(socket[0], line, &len);
|
||||||
|
|
||||||
|
/* 每帧第0行打印一次，确认帧号和socket状态 */
|
||||||
|
if (idx == 0)
|
||||||
|
printf("[DVP] frame=%lu socket=%d\r\n", frame_count, socket[0]);
|
||||||
|
}
|
||||||
|
else if (idx == 0 && socket[0] == 0xFF)
|
||||||
|
{
|
||||||
|
/* socket 未连接时提示 */
|
||||||
|
printf("[DVP] frame=%lu waiting for TCP...\r\n", frame_count);
|
||||||
|
}
|
||||||
|
memset(line, 0, BYTES_PER_LINE);
|
||||||
|
}
|
||||||
|
|
||||||
|
void DVP_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||||
|
void DVP_IRQHandler(void)
|
||||||
|
{
|
||||||
|
if (DVP->IFR & RB_DVP_IF_STR_FRM)
|
||||||
|
{
|
||||||
|
DVP->IFR = RB_DVP_IF_STR_FRM;
|
||||||
|
current_line_idx = 0;
|
||||||
|
frame_count++;
|
||||||
|
}
|
||||||
|
if (DVP->IFR & RB_DVP_IF_ROW_DONE)
|
||||||
|
{
|
||||||
|
DVP->IFR = RB_DVP_IF_ROW_DONE;
|
||||||
|
Ready_Line_Ptr = (DVP->CR1 & RB_DVP_BUF_TOG) ? DMA_LineBuf0 : DMA_LineBuf1;
|
||||||
|
current_line_idx++;
|
||||||
|
Line_Ready_Flag = 1;
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,18 @@
|
|||||||
|
#ifndef DVP_H_
|
||||||
|
#define DVP_H_
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
#define SENSOR_WIDTH 256
|
||||||
|
#define SENSOR_HEIGHT 192
|
||||||
|
#define SENSOR_TOTAL_LINES (SENSOR_HEIGHT + 1) // +1 参数行
|
||||||
|
#define BYTES_PER_LINE (SENSOR_WIDTH * 2) // 每行512字节
|
||||||
|
|
||||||
|
#define ALARM_TEMP_RAW 8000 // 80.00℃ (raw/100)
|
||||||
|
|
||||||
|
extern volatile uint8_t Line_Ready_Flag;
|
||||||
|
extern volatile uint8_t *Ready_Line_Ptr;
|
||||||
|
extern volatile uint32_t current_line_idx;
|
||||||
|
|
||||||
|
void DVP_Init(void);
|
||||||
|
void DVP_Task(void);
|
||||||
|
#endif
|
||||||
@@ -0,0 +1 @@
|
|||||||
|
ENTRY( _start )␍␍__stack_size = 2048;␍␍PROVIDE( _stack_size = __stack_size );␍␍␍MEMORY␍{␍ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 192K␍ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K␍}␍␍␍SECTIONS␍{␍␍ .init :␍ {␍ _sinit = .;␍ . = ALIGN(4);␍ KEEP(*(SORT_NONE(.init)))␍ . = ALIGN(4);␍ _einit = .;␍ } >FLASH AT>FLASH␍␍ .vector :␍ {␍ *(.vector);␍ . = ALIGN(64);␍ } >FLASH AT>FLASH␍␍ .text :␍ {␍ . = ALIGN(4);␍ *(.text)␍ *(.text.*)␍ *(.rodata)␍ *(.rodata*)␍ *(.gnu.linkonce.t.*)␍ . = ALIGN(4);␍ } >FLASH AT>FLASH ␍␍ .fini :␍ {␍ KEEP(*(SORT_NONE(.fini)))␍ . = ALIGN(4);␍ } >FLASH AT>FLASH␍␍ PROVIDE( _etext = . );␍ PROVIDE( _eitcm = . ); ␍␍ .preinit_array :␍ {␍ PROVIDE_HIDDEN (__preinit_array_start = .);␍ KEEP (*(.preinit_array))␍ PROVIDE_HIDDEN (__preinit_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .init_array :␍ {␍ PROVIDE_HIDDEN (__init_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))␍ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))␍ PROVIDE_HIDDEN (__init_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .fini_array :␍ {␍ PROVIDE_HIDDEN (__fini_array_start = .);␍ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))␍ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))␍ PROVIDE_HIDDEN (__fini_array_end = .);␍ } >FLASH AT>FLASH ␍ ␍ .ctors :␍ {␍ /* gcc uses crtbegin.o to find the start of␍ the constructors, so we make sure it is␍ first. Because this is a wildcard, it␍ doesn't matter if the user does not␍ actually link against crtbegin.o; the␍ linker won't look for a file to match a␍ wildcard. The wildcard also means that it␍ doesn't matter which directory crtbegin.o␍ is in. */␍ KEEP (*crtbegin.o(.ctors))␍ KEEP (*crtbegin?.o(.ctors))␍ /* We don't want to include the .ctor section from␍ the crtend.o file until after the sorted ctors.␍ The .ctor section from the crtend file contains the␍ end of ctors marker and it must be last */␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))␍ KEEP (*(SORT(.ctors.*)))␍ KEEP (*(.ctors))␍ } >FLASH AT>FLASH ␍ ␍ .dtors :␍ {␍ KEEP (*crtbegin.o(.dtors))␍ KEEP (*crtbegin?.o(.dtors))␍ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))␍ KEEP (*(SORT(.dtors.*)))␍ KEEP (*(.dtors))␍ } >FLASH AT>FLASH ␍␍ .dalign :␍ {␍ . = ALIGN(4);␍ PROVIDE(_data_vma = .);␍ } >RAM AT>FLASH ␍␍ .dlalign :␍ {␍ . = ALIGN(4); ␍ PROVIDE(_data_lma = .);␍ } >FLASH AT>FLASH␍␍ .data :␍ {␍ *(.gnu.linkonce.r.*)␍ *(.data .data.*)␍ *(.gnu.linkonce.d.*)␍ . = ALIGN(8);␍ PROVIDE( __global_pointer$ = . + 0x800 );␍ *(.sdata .sdata.*)␍ *(.sdata2.*)␍ *(.gnu.linkonce.s.*)␍ . = ALIGN(8);␍ *(.srodata.cst16)␍ *(.srodata.cst8)␍ *(.srodata.cst4)␍ *(.srodata.cst2)␍ *(.srodata .srodata.*)␍ . = ALIGN(4);␍ PROVIDE( _edata = .);␍ } >RAM AT>FLASH␍␍ .bss :␍ {␍ . = ALIGN(4);␍ PROVIDE( _sbss = .);␍ *(.sbss*)␍ *(.gnu.linkonce.sb.*)␍ *(.bss*)␍ *(.gnu.linkonce.b.*) ␍ *(COMMON*)␍ . = ALIGN(4);␍ PROVIDE( _ebss = .);␍ } >RAM AT>FLASH␍␍ PROVIDE( _end = _ebss);␍ PROVIDE( end = . );␍␍ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :␍ {␍ PROVIDE( _heap_end = . );␍ . = ALIGN(4);␍ PROVIDE(_susrstack = . );␍ . = . + __stack_size;␍ PROVIDE( _eusrstack = .);␍ } >RAM ␍␍}␍␍␍␍
|
||||||
@@ -0,0 +1,175 @@
|
|||||||
|
/********************************** (C) COPYRIGHT ************* ******************
|
||||||
|
* File Name : eth_driver.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.3.0
|
||||||
|
* Date : 2022/06/02
|
||||||
|
* Description : This file contains the headers of the ETH Driver.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __ETH_DRIVER__
|
||||||
|
#define __ETH_DRIVER__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "debug.h"
|
||||||
|
#include "wchnet.h"
|
||||||
|
|
||||||
|
/* 1: interrupt 0: polling in RMII or RGMII mode */
|
||||||
|
#define LINK_STAT_ACQUISITION_METHOD 0
|
||||||
|
|
||||||
|
#define PHY_ADDRESS 1
|
||||||
|
|
||||||
|
#define ETH_DMARxDesc_FrameLengthShift 16
|
||||||
|
|
||||||
|
#define ROM_CFG_USERADR_ID 0x1FFFF7E8
|
||||||
|
|
||||||
|
#define PHY_LINK_TASK_PERIOD 50
|
||||||
|
|
||||||
|
#define PHY_ANLPAR_SELECTOR_FIELD 0x1F
|
||||||
|
#define PHY_ANLPAR_SELECTOR_VALUE 0x01 /* 5B'00001 */
|
||||||
|
|
||||||
|
#define PHY_LINK_INIT 0x00
|
||||||
|
#define PHY_LINK_SUC_P (1<<0)
|
||||||
|
#define PHY_LINK_SUC_N (1<<1)
|
||||||
|
#define PHY_LINK_WAIT_SUC (1<<7)
|
||||||
|
|
||||||
|
#define PHY_PN_SWITCH_P (0<<2)
|
||||||
|
#define PHY_PN_SWITCH_N (1<<2)
|
||||||
|
#define PHY_PN_SWITCH_AUTO (2<<2)
|
||||||
|
|
||||||
|
#ifndef WCHNETTIMERPERIOD
|
||||||
|
#define WCHNETTIMERPERIOD 10 /* Timer period, in Ms. */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define GPIO_Output(a,b) \
|
||||||
|
GPIO_InitStructure.GPIO_Pin = b;\
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;\
|
||||||
|
GPIO_Init(a, &GPIO_InitStructure)
|
||||||
|
|
||||||
|
#define GPIO_Input(a,b) \
|
||||||
|
GPIO_InitStructure.GPIO_Pin = b;\
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;\
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;\
|
||||||
|
GPIO_Init(a, &GPIO_InitStructure)
|
||||||
|
|
||||||
|
#define QUERY_STAT_FLAG ((LastQueryPhyTime == (LocalTime / 1000)) ? 0 : 1)
|
||||||
|
|
||||||
|
#define ACCELERATE_LINK_PROCESS() do{\
|
||||||
|
if((TRDetectStep < 2) && (ETH_ReadPHYRegister(gPHYAddress, PHY_ANLPAR) & PHY_ANLPAR_SELECTOR_FIELD))\
|
||||||
|
LinkTaskPeriod = 0;\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
#define UPDATE_LINKTASKPERIOD() do{\
|
||||||
|
if(TRDetectStep == 1)\
|
||||||
|
{\
|
||||||
|
RandVal = RandVal * 214017 + 2531017;\
|
||||||
|
LinkTaskPeriod = RandVal%100 + 50;\
|
||||||
|
}\
|
||||||
|
else {\
|
||||||
|
LinkTaskPeriod = 50;\
|
||||||
|
}\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
#define PHY_RESTART_AUTONEGOTIATION() do{\
|
||||||
|
RegVal = ETH_ReadPHYRegister(gPHYAddress, PHY_BCR);\
|
||||||
|
RegVal &= ~0x01;\
|
||||||
|
RegVal |= PHY_Restart_AutoNegotiation;\
|
||||||
|
ETH_WritePHYRegister( gPHYAddress, PHY_BCR, RegVal);\
|
||||||
|
RegVal = ETH_ReadPHYRegister(gPHYAddress, PHY_BCR);\
|
||||||
|
RegVal |= 0x03 | PHY_Restart_AutoNegotiation;\
|
||||||
|
ETH_WritePHYRegister( gPHYAddress, PHY_BCR, RegVal);\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
#define PHY_TR_SWITCH() do{\
|
||||||
|
phy_mdix = ETH_ReadPHYRegister(gPHYAddress, PHY_MDIX);\
|
||||||
|
if(phy_mdix & 0x01)\
|
||||||
|
{\
|
||||||
|
phy_mdix &= ~0x03;\
|
||||||
|
phy_mdix |= 1 << 1;\
|
||||||
|
}\
|
||||||
|
else\
|
||||||
|
{\
|
||||||
|
phy_mdix &= ~0x03;\
|
||||||
|
phy_mdix |= 1 << 0;\
|
||||||
|
}\
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_MDIX, phy_mdix);\
|
||||||
|
PHY_RESTART_AUTONEGOTIATION();\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
#define PHY_TR_REVERSE() do{\
|
||||||
|
if(phyStatus)\
|
||||||
|
{\
|
||||||
|
RegVal = ETH_ReadPHYRegister(gPHYAddress, PHY_MDIX);\
|
||||||
|
if(RegVal & 0x01)\
|
||||||
|
{\
|
||||||
|
RegVal &= ~0x03;\
|
||||||
|
RegVal |= 1 << 1;\
|
||||||
|
}\
|
||||||
|
else{\
|
||||||
|
RegVal &= ~0x03;\
|
||||||
|
RegVal |= 1 << 0;\
|
||||||
|
}\
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_MDIX, RegVal);\
|
||||||
|
}\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
#define PHY_PN_SWITCH(PNMode) do{\
|
||||||
|
if(PNMode == PHY_PN_SWITCH_AUTO)\
|
||||||
|
{\
|
||||||
|
phyPN = PHY_PN_SWITCH_AUTO;\
|
||||||
|
}\
|
||||||
|
else{\
|
||||||
|
phyPN = (ETH_ReadPHYRegister(gPHYAddress, PHY_MDIX) & (~(0x03 << 2))) | PNMode;\
|
||||||
|
}\
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_MDIX, phyPN);\
|
||||||
|
phyPN = PNMode;\
|
||||||
|
PHY_RESTART_AUTONEGOTIATION();\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
#define PHY_NEGOTIATION_PARAM_INIT() do{\
|
||||||
|
phyStatus = 0;\
|
||||||
|
phySucCnt = 0;\
|
||||||
|
phyLinkCnt = 0;\
|
||||||
|
TRDetectStep = 0;\
|
||||||
|
PhyPolarityDetect = 0;\
|
||||||
|
phyLinkStatus = PHY_LINK_INIT;\
|
||||||
|
phyPN = PHY_PN_SWITCH_AUTO;\
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_MDIX, phyPN);\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
#define PHY_LINK_RESET() do{\
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_BCR, PHY_Reset);\
|
||||||
|
PHY_NEGOTIATION_PARAM_INIT();\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
#define LAST_NEGO_STAT 1 //0:auto-negotiate 1:Parallel detection
|
||||||
|
#define TURN_PN_POLARITY (1<<1) //0:P polarity 1:N polarity
|
||||||
|
|
||||||
|
extern ETH_DMADESCTypeDef *DMATxDescToSet;
|
||||||
|
extern ETH_DMADESCTypeDef *DMARxDescToGet;
|
||||||
|
extern SOCK_INF SocketInf[ ];
|
||||||
|
|
||||||
|
#define PHY_PAG_SEL 0x1F
|
||||||
|
|
||||||
|
void ETH_PHYLink( void );
|
||||||
|
void WCHNET_ETHIsr( void );
|
||||||
|
void WCHNET_MainTask( void );
|
||||||
|
void ETH_LedConfiguration(void);
|
||||||
|
void ETH_Init( uint8_t *macAddr );
|
||||||
|
void ETH_LedLinkSet( uint8_t mode );
|
||||||
|
void ETH_LedDataSet( uint8_t mode );
|
||||||
|
void WCHNET_TimeIsr( uint16_t timperiod );
|
||||||
|
void ETH_Configuration( uint8_t *macAddr );
|
||||||
|
uint8_t ETH_LibInit( uint8_t *ip, uint8_t *gwip, uint8_t *mask, uint8_t *macaddr);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
@@ -0,0 +1,940 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : eth_driver.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.3.0
|
||||||
|
* Date : 2022/06/02
|
||||||
|
* Description : eth program body.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#include "string.h"
|
||||||
|
#include "eth_driver.h"
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB]; /* MAC receive descriptor, 4-byte aligned*/
|
||||||
|
__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB]; /* MAC send descriptor, 4-byte aligned */
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) uint8_t MACRxBuf[ETH_RXBUFNB*ETH_RX_BUF_SZE]; /* MAC receive buffer, 4-byte aligned */
|
||||||
|
__attribute__((__aligned__(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE]; /* MAC send buffer, 4-byte aligned */
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) SOCK_INF SocketInf[WCHNET_MAX_SOCKET_NUM]; /* Socket information table, 4-byte alignment */
|
||||||
|
const uint16_t MemNum[8] = {WCHNET_NUM_IPRAW,
|
||||||
|
WCHNET_NUM_UDP,
|
||||||
|
WCHNET_NUM_TCP,
|
||||||
|
WCHNET_NUM_TCP_LISTEN,
|
||||||
|
WCHNET_NUM_TCP_SEG,
|
||||||
|
WCHNET_NUM_IP_REASSDATA,
|
||||||
|
WCHNET_NUM_PBUF,
|
||||||
|
WCHNET_NUM_POOL_BUF
|
||||||
|
};
|
||||||
|
const uint16_t MemSize[8] = {WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IPRAW_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_UDP_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB_LISTEN),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_SEG),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IP_REASSDATA),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF) + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_POOL_BUF)
|
||||||
|
};
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Memp_Memory[WCHNET_MEMP_SIZE];
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Mem_Heap_Memory[WCHNET_RAM_HEAP_SIZE];
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Mem_ArpTable[WCHNET_RAM_ARP_TABLE_SIZE];
|
||||||
|
|
||||||
|
uint16_t gPHYAddress;
|
||||||
|
uint32_t volatile LocalTime;
|
||||||
|
uint32_t ChipId = 0;
|
||||||
|
|
||||||
|
ETH_DMADESCTypeDef *pDMARxSet;
|
||||||
|
ETH_DMADESCTypeDef *pDMATxSet;
|
||||||
|
|
||||||
|
/* PHY negotiation function */
|
||||||
|
uint8_t phyLinkStatus = 0;
|
||||||
|
uint8_t phyStatus = 0;
|
||||||
|
uint8_t phyLinkCnt = 0;
|
||||||
|
uint8_t phySucCnt = 0;
|
||||||
|
uint8_t phyPN = PHY_PN_SWITCH_AUTO;
|
||||||
|
uint8_t TRDetectStep = 0;
|
||||||
|
uint8_t TRDetectCnt = 0;
|
||||||
|
uint8_t LinkTaskPeriod = 50;
|
||||||
|
uint32_t RandVal = 0;
|
||||||
|
uint8_t volatile phyLinkReset;
|
||||||
|
uint32_t volatile phyLinkTime;
|
||||||
|
|
||||||
|
/* PHY receive processing */
|
||||||
|
uint8_t ReInitMACFlag = 0;
|
||||||
|
uint8_t PhyPolarityDetect = 0;
|
||||||
|
uint32_t LinkSuccTime = 0;
|
||||||
|
|
||||||
|
/*Parameters used when connecting to
|
||||||
|
* devices that do not support auto-negotiation.*/
|
||||||
|
uint8_t phyNegoStat = 0;
|
||||||
|
uint32_t phyNegoLinkTime = 0;
|
||||||
|
|
||||||
|
extern u8 MACAddr[6];
|
||||||
|
void ReInitMACReg(void);
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_GetMacAddr
|
||||||
|
*
|
||||||
|
* @brief Get the MAC address
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_GetMacAddr( uint8_t *p )
|
||||||
|
{
|
||||||
|
uint8_t i;
|
||||||
|
uint8_t *macaddr=(uint8_t *)(ROM_CFG_USERADR_ID+5);
|
||||||
|
|
||||||
|
for(i=0;i<6;i++)
|
||||||
|
{
|
||||||
|
*p = *macaddr;
|
||||||
|
p++;
|
||||||
|
macaddr--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_TimeIsr
|
||||||
|
*
|
||||||
|
* @brief
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_TimeIsr( uint16_t timperiod )
|
||||||
|
{
|
||||||
|
LocalTime += timperiod;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_PhyPNProcess
|
||||||
|
*
|
||||||
|
* @brief Phy PN Polarity related processing
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_PhyPNProcess(void)
|
||||||
|
{
|
||||||
|
uint32_t PhyVal;
|
||||||
|
|
||||||
|
LinkSuccTime = LocalTime;
|
||||||
|
if((ETH->MMCRGUFCR == 0) && (ETH->MMCRFCECR >= 3))
|
||||||
|
{
|
||||||
|
PhyVal = ETH_ReadPHYRegister(gPHYAddress, PHY_MDIX);
|
||||||
|
if((PhyVal >> 2) & 0x01)
|
||||||
|
PhyVal &= ~(3 << 2); //change PHY PN Polarity to normal
|
||||||
|
else
|
||||||
|
PhyVal |= 1 << 2; //change PHY PN Polarity to reverse
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_MDIX, PhyVal);
|
||||||
|
ETH->MMCCR |= ETH_MMCCR_CR; //Counters Reset
|
||||||
|
while(ETH->MMCCR & ETH_MMCCR_CR); //Wait for counters reset to complete
|
||||||
|
}
|
||||||
|
if(ETH->MMCRGUFCR != 0)
|
||||||
|
{
|
||||||
|
PhyPolarityDetect = 0;
|
||||||
|
/* enable Filter function */
|
||||||
|
ETH->MACFFR &= ~(ETH_ReceiveAll_Enable | ETH_PromiscuousMode_Enable);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_RecProcess
|
||||||
|
*
|
||||||
|
* @brief Receiving related processing
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_RecProcess(void)
|
||||||
|
{
|
||||||
|
if(((ChipId & 0xf0) == 0x20) && \
|
||||||
|
((ETH->DMAMFBOCR & 0x1FFE0000) != 0))
|
||||||
|
{
|
||||||
|
ReInitMACReg();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_LinkProcess
|
||||||
|
*
|
||||||
|
* @brief link process.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_LinkProcess( void )
|
||||||
|
{
|
||||||
|
uint16_t phy_anlpar, phy_bmsr, phy_mdix, RegVal;
|
||||||
|
|
||||||
|
phy_anlpar = ETH_ReadPHYRegister(gPHYAddress, PHY_ANLPAR);
|
||||||
|
phy_bmsr = ETH_ReadPHYRegister( gPHYAddress, PHY_BMSR);
|
||||||
|
|
||||||
|
if( (phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD) )
|
||||||
|
{
|
||||||
|
if(TRDetectStep == 0)
|
||||||
|
{
|
||||||
|
TRDetectStep = 1;
|
||||||
|
TRDetectCnt = 1;
|
||||||
|
PHY_TR_SWITCH();
|
||||||
|
LinkTaskPeriod = RandVal%100 + 50;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
else if(TRDetectStep == 1)
|
||||||
|
{
|
||||||
|
TRDetectStep = 2;
|
||||||
|
TRDetectCnt = 0;
|
||||||
|
}
|
||||||
|
if( !(phyLinkStatus&PHY_LINK_WAIT_SUC) )
|
||||||
|
{
|
||||||
|
if( phyPN == PHY_PN_SWITCH_AUTO )
|
||||||
|
{
|
||||||
|
PHY_PN_SWITCH(PHY_PN_SWITCH_P);
|
||||||
|
}
|
||||||
|
else if( phyPN == PHY_PN_SWITCH_P )
|
||||||
|
{
|
||||||
|
phyLinkStatus = PHY_LINK_WAIT_SUC;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
phyLinkStatus = PHY_LINK_WAIT_SUC;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else{
|
||||||
|
if((phySucCnt++ == 5) && ((phy_bmsr&(1<<5)) == 0))
|
||||||
|
{
|
||||||
|
phySucCnt = 0;
|
||||||
|
if(phyPN == PHY_PN_SWITCH_N)
|
||||||
|
PHY_PN_SWITCH(PHY_PN_SWITCH_P);
|
||||||
|
else PHY_PN_SWITCH(PHY_PN_SWITCH_N);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
phyLinkCnt = 0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(TRDetectStep == 1)
|
||||||
|
{
|
||||||
|
TRDetectCnt++;
|
||||||
|
if(TRDetectCnt == 8)
|
||||||
|
{
|
||||||
|
TRDetectCnt = 0;
|
||||||
|
TRDetectStep = 0;
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_MDIX, PHY_PN_SWITCH_AUTO);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
PHY_TR_SWITCH();
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if( phyLinkStatus == PHY_LINK_WAIT_SUC )
|
||||||
|
{
|
||||||
|
if(phyLinkCnt++ == 15 )
|
||||||
|
{
|
||||||
|
phyLinkCnt = 0;
|
||||||
|
phySucCnt = 0;
|
||||||
|
TRDetectStep = 0;
|
||||||
|
phyLinkStatus = PHY_LINK_INIT;
|
||||||
|
PHY_PN_SWITCH(PHY_PN_SWITCH_AUTO);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if( phyPN == PHY_PN_SWITCH_P )
|
||||||
|
{
|
||||||
|
if(phyLinkCnt++ == 4 )
|
||||||
|
{
|
||||||
|
phyLinkCnt = 0;
|
||||||
|
PHY_PN_SWITCH(PHY_PN_SWITCH_N);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if( phyPN == PHY_PN_SWITCH_N )
|
||||||
|
{
|
||||||
|
if(phyLinkCnt++ == 15 )
|
||||||
|
{
|
||||||
|
phyLinkCnt = 0;
|
||||||
|
phySucCnt = 0;
|
||||||
|
TRDetectStep = 0;
|
||||||
|
phyLinkStatus = PHY_LINK_INIT;
|
||||||
|
PHY_PN_SWITCH(PHY_PN_SWITCH_AUTO);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else{
|
||||||
|
if(phyLinkCnt++ == (5000 / PHY_LINK_TASK_PERIOD))
|
||||||
|
PHY_LINK_RESET( );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_HandlePhyNegotiation
|
||||||
|
*
|
||||||
|
* @brief Handle PHY Negotiation.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_HandlePhyNegotiation(void)
|
||||||
|
{
|
||||||
|
if(phyLinkReset) /* After the PHY link is disconnected, wait 500ms before turning on the PHY clock*/
|
||||||
|
{
|
||||||
|
if( LocalTime - phyLinkTime >= 500 )
|
||||||
|
{
|
||||||
|
phyLinkReset = 0;
|
||||||
|
EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN;
|
||||||
|
PHY_LINK_RESET();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
if( !phyStatus ) /* Handling PHY Negotiation Exceptions */
|
||||||
|
{
|
||||||
|
ACCELERATE_LINK_PROCESS();
|
||||||
|
if( LocalTime - phyLinkTime >= LinkTaskPeriod )
|
||||||
|
{
|
||||||
|
UPDATE_LINKTASKPERIOD();
|
||||||
|
phyLinkTime = LocalTime;
|
||||||
|
WCHNET_LinkProcess( );
|
||||||
|
}
|
||||||
|
if(ReInitMACFlag) ReInitMACFlag = 0;
|
||||||
|
}
|
||||||
|
else{ /* PHY link complete */
|
||||||
|
if(ReInitMACFlag)
|
||||||
|
{
|
||||||
|
if( LocalTime - phyLinkTime >= 5 * PHY_LINK_TASK_PERIOD ){
|
||||||
|
u32 phy_stat;
|
||||||
|
ReInitMACFlag = 0;
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_BMSR);
|
||||||
|
if((phy_stat&PHY_Linked_Status) == 0)
|
||||||
|
{
|
||||||
|
WCHNET_PhyStatus( phy_stat );
|
||||||
|
PHY_LINK_RESET();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if(PhyPolarityDetect)
|
||||||
|
{
|
||||||
|
if( LocalTime - LinkSuccTime >= 2 * PHY_LINK_TASK_PERIOD )
|
||||||
|
{
|
||||||
|
WCHNET_PhyPNProcess();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_MainTask
|
||||||
|
*
|
||||||
|
* @brief library main task function
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_MainTask(void)
|
||||||
|
{
|
||||||
|
WCHNET_NetInput( ); /* Ethernet data input */
|
||||||
|
WCHNET_PeriodicHandle( ); /* Protocol stack time-related task processing */
|
||||||
|
WCHNET_HandlePhyNegotiation();
|
||||||
|
WCHNET_RecProcess();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LedLinkSet
|
||||||
|
*
|
||||||
|
* @brief set eth link led,setbit 0 or 1,the link led turn on or turn off
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_LedLinkSet( uint8_t mode )
|
||||||
|
{
|
||||||
|
if( mode == LED_OFF )
|
||||||
|
{
|
||||||
|
GPIO_SetBits(GPIOC, GPIO_Pin_0);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
GPIO_ResetBits(GPIOC, GPIO_Pin_0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LedDataSet
|
||||||
|
*
|
||||||
|
* @brief set eth data led,setbit 0 or 1,the data led turn on or turn off
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_LedDataSet( uint8_t mode )
|
||||||
|
{
|
||||||
|
if( mode == LED_OFF )
|
||||||
|
{
|
||||||
|
GPIO_SetBits(GPIOC, GPIO_Pin_1);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
GPIO_ResetBits(GPIOC, GPIO_Pin_1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LedConfiguration
|
||||||
|
*
|
||||||
|
* @brief set eth data and link led pin
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_LedConfiguration(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO={0};
|
||||||
|
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC,ENABLE);
|
||||||
|
GPIO.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1;
|
||||||
|
GPIO.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||||
|
GPIO.GPIO_Speed = GPIO_Speed_50MHz;
|
||||||
|
GPIO_Init(GPIOC,&GPIO);
|
||||||
|
ETH_LedDataSet(LED_OFF);
|
||||||
|
ETH_LedLinkSet(LED_OFF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_SetClock
|
||||||
|
*
|
||||||
|
* @brief Set ETH Clock(60MHZ).
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_SetClock(void)
|
||||||
|
{
|
||||||
|
RCC_PLL3Cmd(DISABLE);
|
||||||
|
RCC_PREDIV2Config(RCC_PREDIV2_Div2); /* HSE = 8M */
|
||||||
|
RCC_PLL3Config(RCC_PLL3Mul_15); /* 4M*15 = 60MHz */
|
||||||
|
RCC_PLL3Cmd(ENABLE);
|
||||||
|
while(RESET == RCC_GetFlagStatus(RCC_FLAG_PLL3RDY));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LinkUpCfg
|
||||||
|
*
|
||||||
|
* @brief When the PHY is connected, configure the relevant functions.
|
||||||
|
*
|
||||||
|
* @param regval BMSR register value
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_LinkUpCfg(uint16_t regval)
|
||||||
|
{
|
||||||
|
WCHNET_PhyStatus( regval );
|
||||||
|
ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M);
|
||||||
|
phyStatus = PHY_Linked_Status;
|
||||||
|
|
||||||
|
/* disable Filter function */
|
||||||
|
ETH->MACFFR |= (ETH_ReceiveAll_Enable | ETH_PromiscuousMode_Enable);
|
||||||
|
|
||||||
|
ETH->MMCCR |= ETH_MMCCR_CR; //Counters Reset
|
||||||
|
while(ETH->MMCCR & ETH_MMCCR_CR); //Wait for counters reset to complete
|
||||||
|
PhyPolarityDetect = 1;
|
||||||
|
LinkSuccTime = LocalTime;
|
||||||
|
ETH_Start( );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_PHYLink
|
||||||
|
*
|
||||||
|
* @brief Configure MAC parameters after the PHY Link is successful.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_PHYLink( void )
|
||||||
|
{
|
||||||
|
u16 phy_bsr, phy_stat, phy_anlpar, phy_bcr;
|
||||||
|
|
||||||
|
phy_bsr = ETH_ReadPHYRegister( gPHYAddress, PHY_BSR);
|
||||||
|
phy_bcr = ETH_ReadPHYRegister( gPHYAddress, PHY_BCR);
|
||||||
|
phy_anlpar = ETH_ReadPHYRegister( gPHYAddress, PHY_ANLPAR);
|
||||||
|
|
||||||
|
if(phy_bsr & PHY_Linked_Status) //LinkUp
|
||||||
|
{
|
||||||
|
if(phy_bcr & PHY_AutoNegotiation) //determine whether auto-negotiation is enable
|
||||||
|
{
|
||||||
|
if(phy_anlpar == 0)
|
||||||
|
{
|
||||||
|
if(phy_bsr & PHY_AutoNego_Complete)
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~ETH_Mode_FullDuplex;
|
||||||
|
ETH_LinkUpCfg(phy_bsr);
|
||||||
|
if((ChipId & 0xf0) == 0x20)
|
||||||
|
{
|
||||||
|
if(phyNegoStat & TURN_PN_POLARITY)
|
||||||
|
{
|
||||||
|
//select N polarity
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_MDIX, PHY_PN_SWITCH_N);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
//select P polarity
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_MDIX, PHY_PN_SWITCH_P);
|
||||||
|
phyNegoStat |= LAST_NEGO_STAT;
|
||||||
|
}
|
||||||
|
phyNegoLinkTime = LocalTime;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else{
|
||||||
|
PHY_LINK_RESET();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
phyNegoStat = 0;
|
||||||
|
if(phy_bsr & PHY_AutoNego_Complete)
|
||||||
|
{
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_STATUS );
|
||||||
|
if( phy_stat & (1<<2) )
|
||||||
|
{
|
||||||
|
ETH->MACCR |= ETH_Mode_FullDuplex;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if( (phy_anlpar&PHY_ANLPAR_SELECTOR_FIELD) != PHY_ANLPAR_SELECTOR_VALUE )
|
||||||
|
{
|
||||||
|
ETH->MACCR |= ETH_Mode_FullDuplex;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~ETH_Mode_FullDuplex;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
ETH_LinkUpCfg(phy_bsr);
|
||||||
|
}
|
||||||
|
else{
|
||||||
|
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
|
||||||
|
phyLinkReset = 1;
|
||||||
|
phyLinkTime = LocalTime;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
ETH->MACCR &= ~ETH_Mode_FullDuplex;
|
||||||
|
ETH_LinkUpCfg(phy_bsr);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else { //LinkDown
|
||||||
|
WCHNET_PhyStatus( phy_bsr );
|
||||||
|
EXTEN->EXTEN_CTR &= ~EXTEN_ETH_10M_EN;
|
||||||
|
phyLinkReset = 1;
|
||||||
|
phyLinkTime = LocalTime;
|
||||||
|
if((ChipId & 0xf0) == 0x20)
|
||||||
|
{
|
||||||
|
if(phyNegoStat & LAST_NEGO_STAT)
|
||||||
|
{
|
||||||
|
if(LocalTime - phyNegoLinkTime < 100)
|
||||||
|
{
|
||||||
|
phyNegoLinkTime = 0;
|
||||||
|
//Clear any existing error count values.
|
||||||
|
ETH->DMAMFBOCR;
|
||||||
|
phyNegoStat ^= TURN_PN_POLARITY;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ReInitMACReg
|
||||||
|
*
|
||||||
|
* @brief Reinitialize MAC register.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ReInitMACReg(void)
|
||||||
|
{
|
||||||
|
uint16_t timeout = 10000;
|
||||||
|
uint16_t RegVal;
|
||||||
|
uint32_t maccr, macmiiar, macffr, machthr, machtlr;
|
||||||
|
uint32_t macfcr, macvlantr, dmaomr;
|
||||||
|
|
||||||
|
/* Wait for sending data to complete */
|
||||||
|
while((ETH->DMASR & (7 << 20)) != ETH_DMA_TransmitProcess_Suspended);
|
||||||
|
|
||||||
|
PHY_TR_REVERSE();
|
||||||
|
|
||||||
|
/* Record the register value */
|
||||||
|
macmiiar = ETH->MACMIIAR;
|
||||||
|
maccr = ETH->MACCR;
|
||||||
|
macffr = ETH->MACFFR;
|
||||||
|
machthr = ETH->MACHTHR;
|
||||||
|
machtlr = ETH->MACHTLR;
|
||||||
|
macfcr = ETH->MACFCR;
|
||||||
|
macvlantr = ETH->MACVLANTR;
|
||||||
|
dmaomr = ETH->DMAOMR;
|
||||||
|
|
||||||
|
/* Software reset */
|
||||||
|
ETH_SoftwareReset();
|
||||||
|
/* Wait for software reset */
|
||||||
|
do{
|
||||||
|
Delay_Us(10);
|
||||||
|
if( !--timeout ) break;
|
||||||
|
}while(ETH->DMABMR & ETH_DMABMR_SR);
|
||||||
|
|
||||||
|
/* Configure MAC address */
|
||||||
|
ETH->MACA0HR = (uint32_t)((MACAddr[5]<<8) | MACAddr[4]);
|
||||||
|
ETH->MACA0LR = (uint32_t)(MACAddr[0] | (MACAddr[1]<<8) | (MACAddr[2]<<16) | (MACAddr[3]<<24));
|
||||||
|
|
||||||
|
/* Mask the interrupt that Tx good frame count counter reaches half the maximum value */
|
||||||
|
ETH->MMCTIMR = ETH_MMCTIMR_TGFM;
|
||||||
|
/* Mask the interrupt that Rx good unicast frames counter reaches half the maximum value */
|
||||||
|
/* Mask the interrupt that Rx crc error counter reaches half the maximum value */
|
||||||
|
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM;
|
||||||
|
|
||||||
|
ETH_DMAITConfig(ETH_DMA_IT_NIS |\
|
||||||
|
ETH_DMA_IT_R |\
|
||||||
|
ETH_DMA_IT_T |\
|
||||||
|
ETH_DMA_IT_AIS |\
|
||||||
|
ETH_DMA_IT_RBU |\
|
||||||
|
ETH_DMA_IT_PHYLINK,\
|
||||||
|
ENABLE);
|
||||||
|
|
||||||
|
ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB);
|
||||||
|
ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB);
|
||||||
|
pDMARxSet = DMARxDscrTab;
|
||||||
|
pDMATxSet = DMATxDscrTab;
|
||||||
|
|
||||||
|
ETH->MACMIIAR = macmiiar;
|
||||||
|
ETH->MACCR = maccr;
|
||||||
|
ETH->MACFFR = macffr;
|
||||||
|
ETH->MACHTHR = machthr;
|
||||||
|
ETH->MACHTLR = machtlr;
|
||||||
|
ETH->MACFCR = macfcr;
|
||||||
|
ETH->MACVLANTR = macvlantr;
|
||||||
|
ETH->DMAOMR = dmaomr;
|
||||||
|
|
||||||
|
ETH_Start( );
|
||||||
|
|
||||||
|
PHY_TR_REVERSE();
|
||||||
|
|
||||||
|
if(!phyStatus)
|
||||||
|
{
|
||||||
|
PHY_LINK_RESET();
|
||||||
|
}
|
||||||
|
|
||||||
|
ReInitMACFlag = 1;
|
||||||
|
phyLinkTime = LocalTime;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_RegInit
|
||||||
|
*
|
||||||
|
* @brief ETH register initialization.
|
||||||
|
*
|
||||||
|
* @param ETH_InitStruct:initialization struct.
|
||||||
|
* PHYAddress:PHY address.
|
||||||
|
*
|
||||||
|
* @return Initialization status.
|
||||||
|
*/
|
||||||
|
uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress )
|
||||||
|
{
|
||||||
|
/* Set the SMI interface clock, set as the main frequency divided by 42 */
|
||||||
|
ETH->MACMIIAR = (uint32_t)ETH_MACMIIAR_CR_Div42;
|
||||||
|
|
||||||
|
/*------------------------ MAC register configuration -------------------------------------------*/
|
||||||
|
ETH->MACCR = (uint32_t)(ETH_InitStruct->ETH_Watchdog |
|
||||||
|
ETH_InitStruct->ETH_Jabber |
|
||||||
|
ETH_InitStruct->ETH_InterFrameGap |
|
||||||
|
ETH_InitStruct->ETH_ChecksumOffload |
|
||||||
|
ETH_InitStruct->ETH_AutomaticPadCRCStrip |
|
||||||
|
ETH_InitStruct->ETH_LoopbackMode |
|
||||||
|
ETH_Internal_Pull_Up_Res_Enable);
|
||||||
|
|
||||||
|
ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
|
||||||
|
ETH_InitStruct->ETH_SourceAddrFilter |
|
||||||
|
ETH_InitStruct->ETH_PassControlFrames |
|
||||||
|
ETH_InitStruct->ETH_BroadcastFramesReception |
|
||||||
|
ETH_InitStruct->ETH_DestinationAddrFilter |
|
||||||
|
ETH_InitStruct->ETH_PromiscuousMode |
|
||||||
|
ETH_InitStruct->ETH_MulticastFramesFilter |
|
||||||
|
ETH_InitStruct->ETH_UnicastFramesFilter);
|
||||||
|
|
||||||
|
ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
|
||||||
|
ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
|
||||||
|
|
||||||
|
ETH->MACFCR = (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
|
||||||
|
ETH_InitStruct->ETH_UnicastPauseFrameDetect |
|
||||||
|
ETH_InitStruct->ETH_ReceiveFlowControl |
|
||||||
|
ETH_InitStruct->ETH_TransmitFlowControl);
|
||||||
|
|
||||||
|
ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
|
||||||
|
ETH_InitStruct->ETH_VLANTagIdentifier);
|
||||||
|
|
||||||
|
ETH->DMAOMR = (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
|
||||||
|
ETH_InitStruct->ETH_TransmitStoreForward |
|
||||||
|
ETH_InitStruct->ETH_ForwardErrorFrames |
|
||||||
|
ETH_InitStruct->ETH_ForwardUndersizedGoodFrames);
|
||||||
|
|
||||||
|
/* Reset the physical layer */
|
||||||
|
ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset);
|
||||||
|
ETH_WritePHYRegister(PHYAddress, PHY_MDIX, PHY_PN_SWITCH_AUTO);
|
||||||
|
return ETH_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_Configuration
|
||||||
|
*
|
||||||
|
* @brief Ethernet configure.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_Configuration( uint8_t *macAddr )
|
||||||
|
{
|
||||||
|
ETH_InitTypeDef ETH_InitStructure;
|
||||||
|
uint16_t timeout = 10000;
|
||||||
|
|
||||||
|
/* Enable Ethernet MAC clock */
|
||||||
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | \
|
||||||
|
RCC_AHBPeriph_ETH_MAC_Tx | \
|
||||||
|
RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);
|
||||||
|
|
||||||
|
gPHYAddress = PHY_ADDRESS;
|
||||||
|
ETH_SetClock( );
|
||||||
|
|
||||||
|
/* Enable internal 10BASE-T PHY*/
|
||||||
|
EXTEN->EXTEN_CTR |= EXTEN_ETH_10M_EN; /* Enable 10M Ethernet physical layer */
|
||||||
|
|
||||||
|
/* Reset ETHERNET on AHB Bus */
|
||||||
|
ETH_DeInit();
|
||||||
|
|
||||||
|
/* Software reset */
|
||||||
|
ETH_SoftwareReset();
|
||||||
|
|
||||||
|
/* Wait for software reset */
|
||||||
|
do{
|
||||||
|
Delay_Us(10);
|
||||||
|
if( !--timeout ) break;
|
||||||
|
}while(ETH->DMABMR & ETH_DMABMR_SR);
|
||||||
|
|
||||||
|
/* ETHERNET Configuration */
|
||||||
|
/*------------------------ MAC -----------------------------------*/
|
||||||
|
ETH_InitStructure.ETH_Watchdog = ETH_Watchdog_Enable;
|
||||||
|
ETH_InitStructure.ETH_Jabber = ETH_Jabber_Enable;
|
||||||
|
ETH_InitStructure.ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
|
||||||
|
#if HARDWARE_CHECKSUM_CONFIG
|
||||||
|
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
|
||||||
|
#else
|
||||||
|
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
|
||||||
|
#endif
|
||||||
|
ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
|
||||||
|
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
|
||||||
|
|
||||||
|
/* Filter function configuration */
|
||||||
|
ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
|
||||||
|
ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
|
||||||
|
ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
|
||||||
|
ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
|
||||||
|
ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
|
||||||
|
ETH_InitStructure.ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
|
||||||
|
ETH_InitStructure.ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
|
||||||
|
ETH_InitStructure.ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
|
||||||
|
|
||||||
|
ETH_InitStructure.ETH_HashTableHigh = 0x0;
|
||||||
|
ETH_InitStructure.ETH_HashTableLow = 0x0;
|
||||||
|
|
||||||
|
/* VLan function configuration */
|
||||||
|
ETH_InitStructure.ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
|
||||||
|
ETH_InitStructure.ETH_VLANTagIdentifier = 0x0;
|
||||||
|
|
||||||
|
/* Flow Control function configuration */
|
||||||
|
ETH_InitStructure.ETH_PauseTime = 0x0;
|
||||||
|
ETH_InitStructure.ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
|
||||||
|
ETH_InitStructure.ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
|
||||||
|
ETH_InitStructure.ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
|
||||||
|
|
||||||
|
/*------------------------ DMA -----------------------------------*/
|
||||||
|
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
||||||
|
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
||||||
|
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
||||||
|
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
||||||
|
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
||||||
|
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable;
|
||||||
|
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable;
|
||||||
|
|
||||||
|
/* Configure Ethernet */
|
||||||
|
ETH_RegInit( Ð_InitStructure, gPHYAddress );
|
||||||
|
|
||||||
|
/* Configure MAC address */
|
||||||
|
ETH->MACA0HR = (uint32_t)((macAddr[5]<<8) | macAddr[4]);
|
||||||
|
ETH->MACA0LR = (uint32_t)(macAddr[0] | (macAddr[1]<<8) | (macAddr[2]<<16) | (macAddr[3]<<24));
|
||||||
|
|
||||||
|
/* Mask the interrupt that Tx good frame count counter reaches half the maximum value */
|
||||||
|
ETH->MMCTIMR = ETH_MMCTIMR_TGFM;
|
||||||
|
/* Mask the interrupt that Rx good unicast frames counter reaches half the maximum value */
|
||||||
|
/* Mask the interrupt that Rx crc error counter reaches half the maximum value */
|
||||||
|
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM;
|
||||||
|
|
||||||
|
ETH_DMAITConfig(ETH_DMA_IT_NIS |\
|
||||||
|
ETH_DMA_IT_R |\
|
||||||
|
ETH_DMA_IT_T |\
|
||||||
|
ETH_DMA_IT_AIS |\
|
||||||
|
ETH_DMA_IT_RBU |\
|
||||||
|
ETH_DMA_IT_PHYLINK,\
|
||||||
|
ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_TxPktChainMode
|
||||||
|
*
|
||||||
|
* @brief Ethernet sends data frames in chain mode.
|
||||||
|
*
|
||||||
|
* @param len Send data length
|
||||||
|
* pBuff send buffer pointer
|
||||||
|
*
|
||||||
|
* @return Send status.
|
||||||
|
*/
|
||||||
|
uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff )
|
||||||
|
{
|
||||||
|
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
||||||
|
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
|
||||||
|
{
|
||||||
|
/* Return ERROR: OWN bit set */
|
||||||
|
return ETH_ERROR;
|
||||||
|
}
|
||||||
|
/* Setting the Frame Length: bits[12:0] */
|
||||||
|
DMATxDescToSet->ControlBufferSize = (len & ETH_DMATxDesc_TBS1);
|
||||||
|
DMATxDescToSet->Buffer1Addr = (uint32_t)pBuff;
|
||||||
|
|
||||||
|
/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
|
||||||
|
#if HARDWARE_CHECKSUM_CONFIG
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_CIC_TCPUDPICMP_Full;
|
||||||
|
#else
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
||||||
|
|
||||||
|
/* Clear TBUS ETHERNET DMA flag */
|
||||||
|
ETH->DMASR = ETH_DMASR_TBUS;
|
||||||
|
/* Resume DMA transmission*/
|
||||||
|
ETH->DMATPDR = 0;
|
||||||
|
|
||||||
|
/* Update the ETHERNET DMA global Tx descriptor with next Tx descriptor */
|
||||||
|
/* Chained Mode */
|
||||||
|
/* Selects the next DMA Tx descriptor list for next buffer to send */
|
||||||
|
DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
|
||||||
|
/* Return SUCCESS */
|
||||||
|
return ETH_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_ETHIsr
|
||||||
|
*
|
||||||
|
* @brief Ethernet Interrupt Service Routine
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WCHNET_ETHIsr(void)
|
||||||
|
{
|
||||||
|
uint32_t int_sta;
|
||||||
|
|
||||||
|
int_sta = ETH->DMASR;
|
||||||
|
if (int_sta & ETH_DMA_IT_AIS)
|
||||||
|
{
|
||||||
|
if (int_sta & ETH_DMA_IT_RBU)
|
||||||
|
{
|
||||||
|
if((ChipId & 0xf0) == 0x10)
|
||||||
|
{
|
||||||
|
((ETH_DMADESCTypeDef *)(((ETH_DMADESCTypeDef *)(ETH->DMACHRDR))->Buffer2NextDescAddr))->Status = ETH_DMARxDesc_OWN;
|
||||||
|
|
||||||
|
/* Resume DMA reception */
|
||||||
|
ETH->DMARPDR = 0;
|
||||||
|
}
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_RBU);
|
||||||
|
}
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_AIS);
|
||||||
|
}
|
||||||
|
|
||||||
|
if( int_sta & ETH_DMA_IT_NIS )
|
||||||
|
{
|
||||||
|
if( int_sta & ETH_DMA_IT_R )
|
||||||
|
{
|
||||||
|
/*If you don't use the Ethernet library,
|
||||||
|
* you can do some data processing operations here*/
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
|
||||||
|
}
|
||||||
|
if( int_sta & ETH_DMA_IT_T )
|
||||||
|
{
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
|
||||||
|
}
|
||||||
|
if( int_sta & ETH_DMA_IT_PHYLINK)
|
||||||
|
{
|
||||||
|
ETH_PHYLink( );
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_PHYLINK);
|
||||||
|
}
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_Init
|
||||||
|
*
|
||||||
|
* @brief Ethernet initialization.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_Init( uint8_t *macAddr )
|
||||||
|
{
|
||||||
|
Delay_Ms(100);
|
||||||
|
ChipId = DBGMCU_GetCHIPID();
|
||||||
|
ETH_LedConfiguration( );
|
||||||
|
RandVal = (macAddr[3]^macAddr[4]^macAddr[5]) * 214017 + 2531017;
|
||||||
|
ETH_Configuration( macAddr );
|
||||||
|
ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB);
|
||||||
|
ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB);
|
||||||
|
pDMARxSet = DMARxDscrTab;
|
||||||
|
pDMATxSet = DMATxDscrTab;
|
||||||
|
NVIC_EnableIRQ(ETH_IRQn);
|
||||||
|
NVIC_SetPriority(ETH_IRQn, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LibInit
|
||||||
|
*
|
||||||
|
* @brief Ethernet library initialization program
|
||||||
|
*
|
||||||
|
* @return command status
|
||||||
|
*/
|
||||||
|
uint8_t ETH_LibInit( uint8_t *ip, uint8_t *gwip, uint8_t *mask, uint8_t *macaddr )
|
||||||
|
{
|
||||||
|
uint8_t s;
|
||||||
|
struct _WCH_CFG cfg;
|
||||||
|
|
||||||
|
memset(&cfg,0,sizeof(cfg));
|
||||||
|
cfg.TxBufSize = ETH_TX_BUF_SZE;
|
||||||
|
cfg.TCPMss = WCHNET_TCP_MSS;
|
||||||
|
cfg.HeapSize = WCHNET_MEM_HEAP_SIZE;
|
||||||
|
cfg.ARPTableNum = WCHNET_NUM_ARP_TABLE;
|
||||||
|
cfg.MiscConfig0 = WCHNET_MISC_CONFIG0;
|
||||||
|
cfg.MiscConfig1 = WCHNET_MISC_CONFIG1;
|
||||||
|
cfg.led_link = ETH_LedLinkSet;
|
||||||
|
cfg.led_data = ETH_LedDataSet;
|
||||||
|
cfg.net_send = ETH_TxPktChainMode;
|
||||||
|
cfg.CheckValid = WCHNET_CFG_VALID;
|
||||||
|
s = WCHNET_ConfigLIB(&cfg);
|
||||||
|
if( s ){
|
||||||
|
return (s);
|
||||||
|
}
|
||||||
|
s = WCHNET_Init(ip,gwip,mask,macaddr);
|
||||||
|
ETH_Init( macaddr );
|
||||||
|
return (s);
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************** endfile @ eth_driver ******************************/
|
||||||
@@ -0,0 +1,794 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : eth_driver.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.3.0
|
||||||
|
* Date : 2022/06/02
|
||||||
|
* Description : eth program body.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#include "string.h"
|
||||||
|
#include "eth_driver.h"
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB]; /* MAC receive descriptor, 4-byte aligned*/
|
||||||
|
__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB]; /* MAC send descriptor, 4-byte aligned */
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) uint8_t MACRxBuf[ETH_RXBUFNB*ETH_RX_BUF_SZE]; /* MAC receive buffer, 4-byte aligned */
|
||||||
|
__attribute__((__aligned__(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE]; /* MAC send buffer, 4-byte aligned */
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) SOCK_INF SocketInf[WCHNET_MAX_SOCKET_NUM]; /* Socket information table, 4-byte alignment */
|
||||||
|
const uint16_t MemNum[8] = {WCHNET_NUM_IPRAW,
|
||||||
|
WCHNET_NUM_UDP,
|
||||||
|
WCHNET_NUM_TCP,
|
||||||
|
WCHNET_NUM_TCP_LISTEN,
|
||||||
|
WCHNET_NUM_TCP_SEG,
|
||||||
|
WCHNET_NUM_IP_REASSDATA,
|
||||||
|
WCHNET_NUM_PBUF,
|
||||||
|
WCHNET_NUM_POOL_BUF
|
||||||
|
};
|
||||||
|
const uint16_t MemSize[8] = {WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IPRAW_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_UDP_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB_LISTEN),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_SEG),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IP_REASSDATA),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF) + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_POOL_BUF)
|
||||||
|
};
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Memp_Memory[WCHNET_MEMP_SIZE];
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Mem_Heap_Memory[WCHNET_RAM_HEAP_SIZE];
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Mem_ArpTable[WCHNET_RAM_ARP_TABLE_SIZE];
|
||||||
|
|
||||||
|
uint16_t gPHYAddress;
|
||||||
|
uint32_t volatile LocalTime;
|
||||||
|
|
||||||
|
ETH_DMADESCTypeDef *pDMARxSet;
|
||||||
|
ETH_DMADESCTypeDef *pDMATxSet;
|
||||||
|
|
||||||
|
volatile uint8_t LinkSta = 0; //0:Link down 1:Link up
|
||||||
|
uint8_t LinkVaildFlag = 0; //0:invalid 1:valid
|
||||||
|
uint8_t AccelerateLinkStep = 0;
|
||||||
|
uint8_t AccelerateLinkTime = 0;
|
||||||
|
uint8_t LinkProcessingStep = 0;
|
||||||
|
uint32_t LinkProcessingTime = 0;
|
||||||
|
uint32_t TaskExecutionTime = 0;
|
||||||
|
u16 LastPhyStat = 0;
|
||||||
|
u32 LastQueryPhyTime = 0;
|
||||||
|
void ETH_LinkDownCfg(void);
|
||||||
|
void PHY_FuncInit(void);
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_GetMacAddr
|
||||||
|
*
|
||||||
|
* @brief Get the MAC address
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_GetMacAddr( uint8_t *p )
|
||||||
|
{
|
||||||
|
uint8_t i;
|
||||||
|
uint8_t *macaddr = (uint8_t *)(ROM_CFG_USERADR_ID+5);
|
||||||
|
|
||||||
|
for(i=0;i<6;i++)
|
||||||
|
{
|
||||||
|
*p = *macaddr;
|
||||||
|
p++;
|
||||||
|
macaddr--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_TimeIsr
|
||||||
|
*
|
||||||
|
* @brief
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_TimeIsr( uint16_t timperiod )
|
||||||
|
{
|
||||||
|
LocalTime += timperiod;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_QueryPhySta
|
||||||
|
*
|
||||||
|
* @brief Query external PHY status
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_QueryPhySta(void)
|
||||||
|
{
|
||||||
|
u16 phy_stat;
|
||||||
|
if(QUERY_STAT_FLAG){ /* Query the PHY link status every 1s */
|
||||||
|
LastQueryPhyTime = LocalTime / 1000;
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BSR );
|
||||||
|
if((phy_stat != LastPhyStat) && (phy_stat != 0xffff)){
|
||||||
|
ETH_PHYLink();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_CheckPHYPN
|
||||||
|
*
|
||||||
|
* @brief check PHY PN polarity
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_CheckPHYPN(uint16_t time)
|
||||||
|
{
|
||||||
|
u16 phy_stat;
|
||||||
|
|
||||||
|
//check PHY PN
|
||||||
|
if((LinkProcessingStep == 0)||(LocalTime >= LinkProcessingTime))
|
||||||
|
{
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x0 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x10);
|
||||||
|
if(phy_stat & (1<<12))
|
||||||
|
{
|
||||||
|
if(LinkProcessingStep == 0)
|
||||||
|
{
|
||||||
|
LinkProcessingStep = 1;
|
||||||
|
LinkProcessingTime = LocalTime + time;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
LinkProcessingStep = 0;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_ANER);
|
||||||
|
if((time == 200) || ((phy_stat & 1) == 0))
|
||||||
|
{
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x0 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x16);
|
||||||
|
phy_stat |= 1<<5;
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x16, phy_stat );
|
||||||
|
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x16);
|
||||||
|
phy_stat &= ~(1<<5);
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x16, phy_stat );
|
||||||
|
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x1E); /* Clear the Interrupt status */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
LinkProcessingStep = 0;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_AccelerateLink
|
||||||
|
*
|
||||||
|
* @brief accelerate Link processing
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_AccelerateLink(void)
|
||||||
|
{
|
||||||
|
uint16_t phy_stat;
|
||||||
|
|
||||||
|
switch(AccelerateLinkStep)
|
||||||
|
{
|
||||||
|
case 0:
|
||||||
|
AccelerateLinkStep++;
|
||||||
|
AccelerateLinkTime = 0;
|
||||||
|
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_PAG_SEL, 0x00 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, 0x18);
|
||||||
|
phy_stat &= ~(1<<15);
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, 0x18, phy_stat );
|
||||||
|
|
||||||
|
//power down
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR);
|
||||||
|
phy_stat |= (1<<11);
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_BCR, phy_stat );
|
||||||
|
|
||||||
|
//decrease Link Time
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_PAG_SEL, 0x00 );
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, 0x13, 0x4 );
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1:
|
||||||
|
if(AccelerateLinkTime++ > 120) //unit:10ms,total time:1.2s~1.5s
|
||||||
|
{
|
||||||
|
AccelerateLinkStep++;
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_PAG_SEL, 0x00 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, 0x18);
|
||||||
|
phy_stat |= 1<<15;
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, 0x18, phy_stat );
|
||||||
|
// power up
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR);
|
||||||
|
phy_stat &= ~(1<<11);
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_BCR, phy_stat );
|
||||||
|
|
||||||
|
Delay_Us(300);
|
||||||
|
PHY_FuncInit();
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2:
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_PAG_SEL, 99 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, 0x19);
|
||||||
|
if((phy_stat & 0xf) == 2)
|
||||||
|
{
|
||||||
|
AccelerateLinkStep++;
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_PAG_SEL, 0x00 );
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, 0x13, 0x0 );
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
/*do nothing*/
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_CheckLinkVaild
|
||||||
|
*
|
||||||
|
* @brief check whether Link is valid
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_CheckLinkVaild(void)
|
||||||
|
{
|
||||||
|
uint16_t phy_stat, phy_bcr;
|
||||||
|
|
||||||
|
if(LinkVaildFlag == 0)
|
||||||
|
{
|
||||||
|
phy_bcr = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR);
|
||||||
|
if((phy_bcr & (1<<13)) == 0) //Do nothing if Link mode is 10M.
|
||||||
|
{
|
||||||
|
LinkVaildFlag = 1;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x10);
|
||||||
|
if((phy_stat & (1<<9)) == 0)
|
||||||
|
{
|
||||||
|
LinkProcessingTime++;
|
||||||
|
if(LinkProcessingTime == 5)
|
||||||
|
{
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
phy_stat = ETH_ReadPHYRegister(gPHYAddress, PHY_BCR);
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_BCR, PHY_Reset );
|
||||||
|
Delay_Us(100);
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_BCR, phy_stat );
|
||||||
|
ETH_LinkDownCfg();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
LinkVaildFlag = 1;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_LinkProcessing
|
||||||
|
*
|
||||||
|
* @brief process Link stage task
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_LinkProcessing(void)
|
||||||
|
{
|
||||||
|
u16 phy_bcr;
|
||||||
|
|
||||||
|
if(LocalTime >= TaskExecutionTime)
|
||||||
|
{
|
||||||
|
TaskExecutionTime = LocalTime + 10; //execution cycle:10ms
|
||||||
|
if(LinkSta == 0) //Link down
|
||||||
|
{
|
||||||
|
phy_bcr = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR);
|
||||||
|
if(phy_bcr & PHY_AutoNegotiation) //auto-negotiation is enabled
|
||||||
|
{
|
||||||
|
WCHNET_CheckPHYPN(300); //check PHY PN
|
||||||
|
WCHNET_AccelerateLink(); //accelerate Link processing
|
||||||
|
}
|
||||||
|
else { //auto-negotiation is disabled
|
||||||
|
if((phy_bcr & (1<<13)) == 0) // 10M
|
||||||
|
{
|
||||||
|
WCHNET_CheckPHYPN(200); //check PHY PN
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else { //Link up
|
||||||
|
WCHNET_CheckLinkVaild(); //check whether Link is valid
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_MainTask
|
||||||
|
*
|
||||||
|
* @brief library main task function
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_MainTask(void)
|
||||||
|
{
|
||||||
|
WCHNET_NetInput( ); /* Ethernet data input */
|
||||||
|
WCHNET_PeriodicHandle( ); /* Protocol stack time-related task processing */
|
||||||
|
WCHNET_QueryPhySta(); /* Query external PHY status */
|
||||||
|
WCHNET_LinkProcessing(); /* process Link stage task */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_SetClock
|
||||||
|
*
|
||||||
|
* @brief Set the Ethernet related clock
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_SetClock(void)
|
||||||
|
{
|
||||||
|
/* Only support HSE_VALUE: 8MHz.
|
||||||
|
* If you select other HSE value,you should
|
||||||
|
* change the configuration below*/
|
||||||
|
RCC_PLL3Cmd(DISABLE);
|
||||||
|
RCC_PREDIV2Config(RCC_PREDIV2_Div1); // HSE = 8M
|
||||||
|
RCC_PLL3Config(RCC_PLL3Mul_12_5); // 8M*12.5 = 100MHz
|
||||||
|
RCC_PLL3Cmd(ENABLE);
|
||||||
|
while(RESET == RCC_GetFlagStatus(RCC_FLAG_PLL3RDY));
|
||||||
|
Delay_Us(300);//Wait for the PHY clock to stabilize
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_RMIIPinInit
|
||||||
|
*
|
||||||
|
* @brief PHY RMII interface GPIO initialization.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_RMIIPinInit(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD|RCC_APB2Periph_GPIOE|RCC_APB2Periph_AFIO, ENABLE);
|
||||||
|
GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII);
|
||||||
|
GPIO_Output(GPIOD, GPIO_Pin_8); /* MDIO */
|
||||||
|
GPIO_Output(GPIOE, GPIO_Pin_15); /* MDC */
|
||||||
|
|
||||||
|
GPIO_Output(GPIOE, GPIO_Pin_8); /* TXEN */
|
||||||
|
GPIO_Output(GPIOE, GPIO_Pin_11); /* TXD0 */
|
||||||
|
GPIO_Output(GPIOE, GPIO_Pin_10); /* TXD1 */
|
||||||
|
|
||||||
|
GPIO_Output(GPIOE, GPIO_Pin_12); /* REFCLK */
|
||||||
|
GPIO_Input(GPIOE, GPIO_Pin_9); /* CRSDV */
|
||||||
|
GPIO_Input(GPIOE, GPIO_Pin_14); /* RXD0 */
|
||||||
|
GPIO_Input(GPIOE, GPIO_Pin_13); /* RXD1 */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LinkUpCfg
|
||||||
|
*
|
||||||
|
* @brief When the PHY is connected, configure the relevant functions.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_LinkUpCfg(void)
|
||||||
|
{
|
||||||
|
uint16_t phy_stat;
|
||||||
|
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR );
|
||||||
|
/* PHY negotiation result */
|
||||||
|
if(phy_stat & (1<<13)) /* 100M */
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M);
|
||||||
|
ETH->MACCR |= ETH_Speed_100M;
|
||||||
|
}
|
||||||
|
else /* 10M */
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M);
|
||||||
|
}
|
||||||
|
if(phy_stat & (1<<8)) /* full duplex */
|
||||||
|
{
|
||||||
|
ETH->MACCR |= ETH_Mode_FullDuplex;
|
||||||
|
}
|
||||||
|
else /* half duplex */
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~ETH_Mode_FullDuplex;
|
||||||
|
}
|
||||||
|
|
||||||
|
LinkSta = 1;
|
||||||
|
AccelerateLinkStep = 0;
|
||||||
|
LinkProcessingStep = 0;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
ETH_Start( );
|
||||||
|
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x0 );
|
||||||
|
phy_stat = 0x0;
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x13, phy_stat );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LinkDownCfg
|
||||||
|
*
|
||||||
|
* @brief When the PHY is disconnected, configure the relevant functions.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_LinkDownCfg(void)
|
||||||
|
{
|
||||||
|
LinkSta = 0;
|
||||||
|
LinkVaildFlag = 0;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_PHYLink
|
||||||
|
*
|
||||||
|
* @brief Configure MAC parameters after the PHY Link is successful.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_PHYLink( void )
|
||||||
|
{
|
||||||
|
u32 phy_stat, phy_anlpar, phy_bcr;
|
||||||
|
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BSR );
|
||||||
|
phy_anlpar = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_ANLPAR);
|
||||||
|
phy_bcr = ETH_ReadPHYRegister( gPHYAddress, PHY_BCR);
|
||||||
|
LastPhyStat = phy_stat;
|
||||||
|
|
||||||
|
WCHNET_PhyStatus( phy_stat );
|
||||||
|
if(phy_stat & PHY_Linked_Status) //LinkUp
|
||||||
|
{
|
||||||
|
if(phy_bcr & PHY_AutoNegotiation)
|
||||||
|
{
|
||||||
|
if(phy_anlpar == 0)
|
||||||
|
{
|
||||||
|
ETH_LinkUpCfg();
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
if(phy_stat & PHY_AutoNego_Complete)
|
||||||
|
{
|
||||||
|
ETH_LinkUpCfg();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
ETH_LinkUpCfg();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else { //LinkDown
|
||||||
|
/*Link down*/
|
||||||
|
ETH_LinkDownCfg();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PHY_FuncInit
|
||||||
|
*
|
||||||
|
* @brief PHY register initialization.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None.
|
||||||
|
*/
|
||||||
|
void PHY_FuncInit(void)
|
||||||
|
{
|
||||||
|
uint16_t regval;
|
||||||
|
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x00 );
|
||||||
|
/* Configure Repeater mode */
|
||||||
|
regval = ETH_ReadPHYRegister(gPHYAddress, 28);
|
||||||
|
regval |= 1<<13;
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 28, regval );
|
||||||
|
|
||||||
|
/*rmii rx&tx clock change */
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x07 );
|
||||||
|
regval = ETH_ReadPHYRegister( gPHYAddress, 16);
|
||||||
|
regval &= ~(0xff<<4);
|
||||||
|
regval |= 0x23<<4;
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 16, regval );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_RegInit
|
||||||
|
*
|
||||||
|
* @brief ETH register initialization.
|
||||||
|
*
|
||||||
|
* @param ETH_InitStruct:initialization struct.
|
||||||
|
* PHYAddress:PHY address.
|
||||||
|
*
|
||||||
|
* @return Initialization status.
|
||||||
|
*/
|
||||||
|
uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress )
|
||||||
|
{
|
||||||
|
/* Set the SMI interface clock, set as the main frequency divided by 42 */
|
||||||
|
ETH->MACMIIAR = (uint32_t)ETH_MACMIIAR_CR_Div42;
|
||||||
|
|
||||||
|
/*------------------------ MAC register configuration -------------------------------------------*/
|
||||||
|
ETH->MACCR = (uint32_t)(ETH_InitStruct->ETH_Watchdog |
|
||||||
|
ETH_InitStruct->ETH_Jabber |
|
||||||
|
ETH_InitStruct->ETH_InterFrameGap |
|
||||||
|
ETH_InitStruct->ETH_ChecksumOffload |
|
||||||
|
ETH_InitStruct->ETH_AutomaticPadCRCStrip |
|
||||||
|
ETH_InitStruct->ETH_LoopbackMode);
|
||||||
|
|
||||||
|
ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
|
||||||
|
ETH_InitStruct->ETH_SourceAddrFilter |
|
||||||
|
ETH_InitStruct->ETH_PassControlFrames |
|
||||||
|
ETH_InitStruct->ETH_BroadcastFramesReception |
|
||||||
|
ETH_InitStruct->ETH_DestinationAddrFilter |
|
||||||
|
ETH_InitStruct->ETH_PromiscuousMode |
|
||||||
|
ETH_InitStruct->ETH_MulticastFramesFilter |
|
||||||
|
ETH_InitStruct->ETH_UnicastFramesFilter);
|
||||||
|
|
||||||
|
ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
|
||||||
|
ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
|
||||||
|
|
||||||
|
ETH->MACFCR = (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
|
||||||
|
ETH_InitStruct->ETH_UnicastPauseFrameDetect |
|
||||||
|
ETH_InitStruct->ETH_ReceiveFlowControl |
|
||||||
|
ETH_InitStruct->ETH_TransmitFlowControl);
|
||||||
|
|
||||||
|
ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
|
||||||
|
ETH_InitStruct->ETH_VLANTagIdentifier);
|
||||||
|
|
||||||
|
ETH->DMAOMR = (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
|
||||||
|
ETH_InitStruct->ETH_TransmitStoreForward |
|
||||||
|
ETH_InitStruct->ETH_ForwardErrorFrames |
|
||||||
|
ETH_InitStruct->ETH_ForwardUndersizedGoodFrames);
|
||||||
|
|
||||||
|
/* Reset the physical layer */
|
||||||
|
ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset);
|
||||||
|
Delay_Ms(1);
|
||||||
|
return ETH_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_Configuration
|
||||||
|
*
|
||||||
|
* @brief Ethernet configure.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_Configuration( uint8_t *macAddr )
|
||||||
|
{
|
||||||
|
ETH_InitTypeDef ETH_InitStructure;
|
||||||
|
uint16_t timeout = 10000;
|
||||||
|
|
||||||
|
/* Enable Ethernet MAC clock */
|
||||||
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | \
|
||||||
|
RCC_AHBPeriph_ETH_MAC_Tx | \
|
||||||
|
RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);
|
||||||
|
|
||||||
|
gPHYAddress = PHY_ADDRESS;
|
||||||
|
|
||||||
|
/* Enable RMII GPIO */
|
||||||
|
ETH_RMIIPinInit();
|
||||||
|
|
||||||
|
/* Set the Ethernet related clock */
|
||||||
|
ETH_SetClock();
|
||||||
|
|
||||||
|
/* Reset ETHERNET on AHB Bus */
|
||||||
|
ETH_DeInit();
|
||||||
|
|
||||||
|
/* Software reset */
|
||||||
|
ETH_SoftwareReset();
|
||||||
|
|
||||||
|
/* Wait for software reset */
|
||||||
|
do{
|
||||||
|
Delay_Us(10);
|
||||||
|
if( !--timeout ) break;
|
||||||
|
}while(ETH->DMABMR & ETH_DMABMR_SR);
|
||||||
|
|
||||||
|
/* ETHERNET Configuration */
|
||||||
|
/*------------------------ MAC -----------------------------------*/
|
||||||
|
ETH_InitStructure.ETH_Watchdog = ETH_Watchdog_Enable;
|
||||||
|
ETH_InitStructure.ETH_Jabber = ETH_Jabber_Enable;
|
||||||
|
ETH_InitStructure.ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
|
||||||
|
#if HARDWARE_CHECKSUM_CONFIG
|
||||||
|
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
|
||||||
|
#else
|
||||||
|
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
|
||||||
|
#endif
|
||||||
|
ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
|
||||||
|
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
|
||||||
|
|
||||||
|
/* Filter function configuration */
|
||||||
|
ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
|
||||||
|
ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
|
||||||
|
ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
|
||||||
|
ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
|
||||||
|
ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
|
||||||
|
ETH_InitStructure.ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
|
||||||
|
ETH_InitStructure.ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
|
||||||
|
ETH_InitStructure.ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
|
||||||
|
|
||||||
|
ETH_InitStructure.ETH_HashTableHigh = 0x0;
|
||||||
|
ETH_InitStructure.ETH_HashTableLow = 0x0;
|
||||||
|
|
||||||
|
/* VLan function configuration */
|
||||||
|
ETH_InitStructure.ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
|
||||||
|
ETH_InitStructure.ETH_VLANTagIdentifier = 0x0;
|
||||||
|
|
||||||
|
/* Flow Control function configuration */
|
||||||
|
ETH_InitStructure.ETH_PauseTime = 0x0;
|
||||||
|
ETH_InitStructure.ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
|
||||||
|
ETH_InitStructure.ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
|
||||||
|
ETH_InitStructure.ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
|
||||||
|
|
||||||
|
/*------------------------ DMA -----------------------------------*/
|
||||||
|
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
||||||
|
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
||||||
|
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
||||||
|
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
||||||
|
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
||||||
|
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable;
|
||||||
|
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable;
|
||||||
|
/* Configure Ethernet */
|
||||||
|
ETH_RegInit( Ð_InitStructure, gPHYAddress );
|
||||||
|
|
||||||
|
/* Configure MAC address */
|
||||||
|
ETH->MACA0HR = (uint32_t)((macAddr[5]<<8) | macAddr[4]);
|
||||||
|
ETH->MACA0LR = (uint32_t)(macAddr[0] | (macAddr[1]<<8) | (macAddr[2]<<16) | (macAddr[3]<<24));
|
||||||
|
|
||||||
|
/* Mask the interrupt that Tx good frame count counter reaches half the maximum value */
|
||||||
|
ETH->MMCTIMR = ETH_MMCTIMR_TGFM;
|
||||||
|
/* Mask the interrupt that Rx good unicast frames counter reaches half the maximum value */
|
||||||
|
/* Mask the interrupt that Rx crc error counter reaches half the maximum value */
|
||||||
|
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM;
|
||||||
|
|
||||||
|
ETH_DMAITConfig(ETH_DMA_IT_NIS |\
|
||||||
|
ETH_DMA_IT_R |\
|
||||||
|
ETH_DMA_IT_T |\
|
||||||
|
ETH_DMA_IT_AIS |\
|
||||||
|
ETH_DMA_IT_RBU,\
|
||||||
|
ENABLE);
|
||||||
|
|
||||||
|
PHY_FuncInit();
|
||||||
|
/*Reads the default value of the PHY_BSR register*/
|
||||||
|
LastPhyStat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BSR );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_TxPktChainMode
|
||||||
|
*
|
||||||
|
* @brief Ethernet sends data frames in chain mode.
|
||||||
|
*
|
||||||
|
* @param len Send data length
|
||||||
|
* pBuff send buffer pointer
|
||||||
|
*
|
||||||
|
* @return Send status.
|
||||||
|
*/
|
||||||
|
uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff )
|
||||||
|
{
|
||||||
|
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
||||||
|
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
|
||||||
|
{
|
||||||
|
/* Return ERROR: OWN bit set */
|
||||||
|
return ETH_ERROR;
|
||||||
|
}
|
||||||
|
/* Setting the Frame Length: bits[12:0] */
|
||||||
|
DMATxDescToSet->ControlBufferSize = (len & ETH_DMATxDesc_TBS1);
|
||||||
|
DMATxDescToSet->Buffer1Addr = (uint32_t)pBuff;
|
||||||
|
|
||||||
|
/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
|
||||||
|
#if HARDWARE_CHECKSUM_CONFIG
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_CIC_TCPUDPICMP_Full;
|
||||||
|
#else
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
||||||
|
|
||||||
|
/* Clear TBUS ETHERNET DMA flag */
|
||||||
|
ETH->DMASR = ETH_DMASR_TBUS;
|
||||||
|
/* Resume DMA transmission*/
|
||||||
|
ETH->DMATPDR = 0;
|
||||||
|
|
||||||
|
/* Update the ETHERNET DMA global Tx descriptor with next Tx descriptor */
|
||||||
|
/* Chained Mode */
|
||||||
|
/* Selects the next DMA Tx descriptor list for next buffer to send */
|
||||||
|
DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
|
||||||
|
/* Return SUCCESS */
|
||||||
|
return ETH_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_ETHIsr
|
||||||
|
*
|
||||||
|
* @brief Ethernet Interrupt Service Routine
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WCHNET_ETHIsr(void)
|
||||||
|
{
|
||||||
|
uint32_t int_sta;
|
||||||
|
|
||||||
|
int_sta = ETH->DMASR;
|
||||||
|
if (int_sta & ETH_DMA_IT_AIS)
|
||||||
|
{
|
||||||
|
if (int_sta & ETH_DMA_IT_RBU)
|
||||||
|
{
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_RBU);
|
||||||
|
}
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_AIS);
|
||||||
|
}
|
||||||
|
|
||||||
|
if( int_sta & ETH_DMA_IT_NIS )
|
||||||
|
{
|
||||||
|
if( int_sta & ETH_DMA_IT_R )
|
||||||
|
{
|
||||||
|
/*If you don't use the Ethernet library,
|
||||||
|
* you can do some data processing operations here*/
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
|
||||||
|
}
|
||||||
|
if( int_sta & ETH_DMA_IT_T )
|
||||||
|
{
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
|
||||||
|
}
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_Init
|
||||||
|
*
|
||||||
|
* @brief Ethernet initialization.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_Init( uint8_t *macAddr )
|
||||||
|
{
|
||||||
|
ETH_Configuration( macAddr );
|
||||||
|
ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB);
|
||||||
|
ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB);
|
||||||
|
pDMARxSet = DMARxDscrTab;
|
||||||
|
pDMATxSet = DMATxDscrTab;
|
||||||
|
NVIC_EnableIRQ(ETH_IRQn);
|
||||||
|
NVIC_SetPriority(ETH_IRQn, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LibInit
|
||||||
|
*
|
||||||
|
* @brief Ethernet library initialization program
|
||||||
|
*
|
||||||
|
* @return command status
|
||||||
|
*/
|
||||||
|
uint8_t ETH_LibInit( uint8_t *ip, uint8_t *gwip, uint8_t *mask, uint8_t *macaddr )
|
||||||
|
{
|
||||||
|
uint8_t s;
|
||||||
|
struct _WCH_CFG cfg;
|
||||||
|
|
||||||
|
memset(&cfg,0,sizeof(cfg));
|
||||||
|
cfg.TxBufSize = ETH_TX_BUF_SZE;
|
||||||
|
cfg.TCPMss = WCHNET_TCP_MSS;
|
||||||
|
cfg.HeapSize = WCHNET_MEM_HEAP_SIZE;
|
||||||
|
cfg.ARPTableNum = WCHNET_NUM_ARP_TABLE;
|
||||||
|
cfg.MiscConfig0 = WCHNET_MISC_CONFIG0;
|
||||||
|
cfg.MiscConfig1 = WCHNET_MISC_CONFIG1;
|
||||||
|
cfg.net_send = ETH_TxPktChainMode;
|
||||||
|
cfg.CheckValid = WCHNET_CFG_VALID;
|
||||||
|
s = WCHNET_ConfigLIB(&cfg);
|
||||||
|
if( s ){
|
||||||
|
return (s);
|
||||||
|
}
|
||||||
|
s = WCHNET_Init(ip,gwip,mask,macaddr);
|
||||||
|
ETH_Init( macaddr );
|
||||||
|
return (s);
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************** endfile @ eth_driver ******************************/
|
||||||
@@ -0,0 +1,876 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : eth_driver.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.3.0
|
||||||
|
* Date : 2022/06/02
|
||||||
|
* Description : eth program body.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#include "string.h"
|
||||||
|
#include "eth_driver.h"
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB]; /* MAC receive descriptor, 4-byte aligned*/
|
||||||
|
__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB]; /* MAC send descriptor, 4-byte aligned */
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) uint8_t MACRxBuf[ETH_RXBUFNB*ETH_RX_BUF_SZE]; /* MAC receive buffer, 4-byte aligned */
|
||||||
|
__attribute__((__aligned__(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE]; /* MAC send buffer, 4-byte aligned */
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) SOCK_INF SocketInf[WCHNET_MAX_SOCKET_NUM]; /* Socket information table, 4-byte alignment */
|
||||||
|
const uint16_t MemNum[8] = {WCHNET_NUM_IPRAW,
|
||||||
|
WCHNET_NUM_UDP,
|
||||||
|
WCHNET_NUM_TCP,
|
||||||
|
WCHNET_NUM_TCP_LISTEN,
|
||||||
|
WCHNET_NUM_TCP_SEG,
|
||||||
|
WCHNET_NUM_IP_REASSDATA,
|
||||||
|
WCHNET_NUM_PBUF,
|
||||||
|
WCHNET_NUM_POOL_BUF
|
||||||
|
};
|
||||||
|
const uint16_t MemSize[8] = {WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IPRAW_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_UDP_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB_LISTEN),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_SEG),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IP_REASSDATA),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF) + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_POOL_BUF)
|
||||||
|
};
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Memp_Memory[WCHNET_MEMP_SIZE];
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Mem_Heap_Memory[WCHNET_RAM_HEAP_SIZE];
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Mem_ArpTable[WCHNET_RAM_ARP_TABLE_SIZE];
|
||||||
|
|
||||||
|
uint16_t gPHYAddress;
|
||||||
|
uint32_t ChipId = 0;
|
||||||
|
uint32_t volatile LocalTime;
|
||||||
|
|
||||||
|
ETH_DMADESCTypeDef *pDMARxSet;
|
||||||
|
ETH_DMADESCTypeDef *pDMATxSet;
|
||||||
|
|
||||||
|
extern u8 MACAddr[6];
|
||||||
|
volatile uint8_t LinkSta = 0; //0:Link down 1:Link up
|
||||||
|
uint8_t LinkVaildFlag = 0; //0:invalid 1:valid
|
||||||
|
uint8_t AccelerateLinkStep = 0;
|
||||||
|
uint8_t AccelerateLinkTime = 0;
|
||||||
|
uint8_t LinkProcessingStep = 0;
|
||||||
|
uint32_t LinkProcessingTime = 0;
|
||||||
|
uint32_t TaskExecutionTime = 0;
|
||||||
|
u16 LastPhyStat = 0;
|
||||||
|
u32 LastQueryPhyTime = 0;
|
||||||
|
void ETH_LinkDownCfg(void);
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_GetMacAddr
|
||||||
|
*
|
||||||
|
* @brief Get the MAC address
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_GetMacAddr( uint8_t *p )
|
||||||
|
{
|
||||||
|
uint8_t i;
|
||||||
|
uint8_t *macaddr = (uint8_t *)(ROM_CFG_USERADR_ID+5);
|
||||||
|
|
||||||
|
for(i=0;i<6;i++)
|
||||||
|
{
|
||||||
|
*p = *macaddr;
|
||||||
|
p++;
|
||||||
|
macaddr--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_TimeIsr
|
||||||
|
*
|
||||||
|
* @brief
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_TimeIsr( uint16_t timperiod )
|
||||||
|
{
|
||||||
|
LocalTime += timperiod;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_QueryPhySta
|
||||||
|
*
|
||||||
|
* @brief Query external PHY status
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_QueryPhySta(void)
|
||||||
|
{
|
||||||
|
u16 phy_stat;
|
||||||
|
if(QUERY_STAT_FLAG){ /* Query the PHY link status every 1s */
|
||||||
|
LastQueryPhyTime = LocalTime / 1000;
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BSR );
|
||||||
|
if((phy_stat != LastPhyStat) && (phy_stat != 0xffff)){
|
||||||
|
ETH_PHYLink();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_CheckPHYPN
|
||||||
|
*
|
||||||
|
* @brief check PHY PN polarity
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_CheckPHYPN(uint16_t time)
|
||||||
|
{
|
||||||
|
u16 phy_stat;
|
||||||
|
|
||||||
|
//check PHY PN
|
||||||
|
if((LinkProcessingStep == 0)||(LocalTime >= LinkProcessingTime))
|
||||||
|
{
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x0 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x10);
|
||||||
|
if(phy_stat & (1<<12))
|
||||||
|
{
|
||||||
|
if(LinkProcessingStep == 0)
|
||||||
|
{
|
||||||
|
LinkProcessingStep = 1;
|
||||||
|
LinkProcessingTime = LocalTime + time;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
LinkProcessingStep = 0;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_ANER);
|
||||||
|
if((time == 200) || ((phy_stat & 1) == 0))
|
||||||
|
{
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x0 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x16);
|
||||||
|
phy_stat |= 1<<5;
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x16, phy_stat );
|
||||||
|
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x16);
|
||||||
|
phy_stat &= ~(1<<5);
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x16, phy_stat );
|
||||||
|
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x1E); /* Clear the Interrupt status */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
LinkProcessingStep = 0;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_AccelerateLink
|
||||||
|
*
|
||||||
|
* @brief accelerate Link processing
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_AccelerateLink(void)
|
||||||
|
{
|
||||||
|
uint16_t phy_stat;
|
||||||
|
|
||||||
|
switch(AccelerateLinkStep)
|
||||||
|
{
|
||||||
|
case 0:
|
||||||
|
AccelerateLinkStep++;
|
||||||
|
AccelerateLinkTime = 0;
|
||||||
|
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_PAG_SEL, 0x00 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, 0x18);
|
||||||
|
phy_stat &= ~(1<<15);
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, 0x18, phy_stat );
|
||||||
|
|
||||||
|
//power down
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR);
|
||||||
|
phy_stat |= (1<<11);
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_BCR, phy_stat );
|
||||||
|
|
||||||
|
//decrease Link Time
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_PAG_SEL, 0x00 );
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, 0x13, 0x4 );
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1:
|
||||||
|
if(AccelerateLinkTime++ > 120) //unit:10ms,total time:1.2s~1.5s
|
||||||
|
{
|
||||||
|
AccelerateLinkStep++;
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_PAG_SEL, 0x00 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, 0x18);
|
||||||
|
phy_stat |= 1<<15;
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, 0x18, phy_stat );
|
||||||
|
// power up
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR);
|
||||||
|
phy_stat &= ~(1<<11);
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_BCR, phy_stat );
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2:
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_PAG_SEL, 99 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, 0x19);
|
||||||
|
if((phy_stat & 0xf) == 2)
|
||||||
|
{
|
||||||
|
AccelerateLinkStep++;
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, PHY_PAG_SEL, 0x00 );
|
||||||
|
ETH_WritePHYRegister(PHY_ADDRESS, 0x13, 0x0 );
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
/*do nothing*/
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_CheckLinkVaild
|
||||||
|
*
|
||||||
|
* @brief check whether Link is valid
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_CheckLinkVaild(void)
|
||||||
|
{
|
||||||
|
uint16_t phy_stat, phy_bcr;
|
||||||
|
|
||||||
|
if(LinkVaildFlag == 0)
|
||||||
|
{
|
||||||
|
phy_bcr = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR);
|
||||||
|
if((phy_bcr & (1<<13)) == 0) //Do nothing if Link mode is 10M.
|
||||||
|
{
|
||||||
|
LinkVaildFlag = 1;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0 );
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x10);
|
||||||
|
if((phy_stat & (1<<9)) == 0)
|
||||||
|
{
|
||||||
|
LinkProcessingTime++;
|
||||||
|
if(LinkProcessingTime == 5)
|
||||||
|
{
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
phy_stat = ETH_ReadPHYRegister(gPHYAddress, PHY_BCR);
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_BCR, PHY_Reset );
|
||||||
|
Delay_Us(100);
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, PHY_BCR, phy_stat );
|
||||||
|
ETH_LinkDownCfg();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
LinkVaildFlag = 1;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_LinkProcessing
|
||||||
|
*
|
||||||
|
* @brief process Link stage task
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_LinkProcessing(void)
|
||||||
|
{
|
||||||
|
u16 phy_bcr;
|
||||||
|
|
||||||
|
if(LocalTime >= TaskExecutionTime)
|
||||||
|
{
|
||||||
|
TaskExecutionTime = LocalTime + 10; //execution cycle:10ms
|
||||||
|
if(LinkSta == 0) //Link down
|
||||||
|
{
|
||||||
|
phy_bcr = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR);
|
||||||
|
if(phy_bcr & PHY_AutoNegotiation) //auto-negotiation is enabled
|
||||||
|
{
|
||||||
|
WCHNET_CheckPHYPN(300); //check PHY PN
|
||||||
|
WCHNET_AccelerateLink(); //accelerate Link processing
|
||||||
|
}
|
||||||
|
else { //auto-negotiation is disabled
|
||||||
|
if((phy_bcr & (1<<13)) == 0) // 10M
|
||||||
|
{
|
||||||
|
WCHNET_CheckPHYPN(200); //check PHY PN
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else { //Link up
|
||||||
|
WCHNET_CheckLinkVaild(); //check whether Link is valid
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_MainTask
|
||||||
|
*
|
||||||
|
* @brief library main task function
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_MainTask(void)
|
||||||
|
{
|
||||||
|
WCHNET_NetInput( ); /* Ethernet data input */
|
||||||
|
WCHNET_PeriodicHandle( ); /* Protocol stack time-related task processing */
|
||||||
|
|
||||||
|
WCHNET_QueryPhySta(); /* Query external PHY status */
|
||||||
|
WCHNET_LinkProcessing(); /* process Link stage task */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_MIIPinInit
|
||||||
|
*
|
||||||
|
* @brief PHY MII interface GPIO initialization.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_MIIPinInit(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);
|
||||||
|
|
||||||
|
GPIO_Output(GPIOA, GPIO_Pin_2); /* MDIO */
|
||||||
|
GPIO_Output(GPIOC, GPIO_Pin_1); /* MDC */
|
||||||
|
|
||||||
|
GPIO_Input(GPIOC, GPIO_Pin_3); /* TXCLK */
|
||||||
|
GPIO_Output(GPIOB, GPIO_Pin_11); /* TXEN */
|
||||||
|
GPIO_Output(GPIOB, GPIO_Pin_12); /* TXD0 */
|
||||||
|
GPIO_Output(GPIOB, GPIO_Pin_13); /* TXD1 */
|
||||||
|
GPIO_Output(GPIOC, GPIO_Pin_2); /* TXD2 */
|
||||||
|
GPIO_Output(GPIOB, GPIO_Pin_8); /* TXD3 */
|
||||||
|
GPIO_Input(GPIOA, GPIO_Pin_1); /* RXC */
|
||||||
|
GPIO_Input(GPIOA, GPIO_Pin_7); /* RXDV */
|
||||||
|
GPIO_Input(GPIOC, GPIO_Pin_4); /* RXD0 */
|
||||||
|
GPIO_Input(GPIOC, GPIO_Pin_5); /* RXD1 */
|
||||||
|
GPIO_Input(GPIOB, GPIO_Pin_0); /* RXD2 */
|
||||||
|
GPIO_Input(GPIOB, GPIO_Pin_1); /* RXD3 */
|
||||||
|
GPIO_Input(GPIOB, GPIO_Pin_10); /* RXER */
|
||||||
|
|
||||||
|
GPIO_Output(GPIOA, GPIO_Pin_0); /* CRS */
|
||||||
|
GPIO_Output(GPIOA, GPIO_Pin_3); /* COL */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LinkUpCfg
|
||||||
|
*
|
||||||
|
* @brief When the PHY is connected, configure the relevant functions.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_LinkUpCfg(void)
|
||||||
|
{
|
||||||
|
uint16_t phy_stat;
|
||||||
|
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BCR );
|
||||||
|
/* PHY negotiation result */
|
||||||
|
if(phy_stat & (1<<13)) /* 100M */
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M);
|
||||||
|
ETH->MACCR |= ETH_Speed_100M;
|
||||||
|
}
|
||||||
|
else /* 10M */
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M);
|
||||||
|
}
|
||||||
|
if(phy_stat & (1<<8)) /* full duplex */
|
||||||
|
{
|
||||||
|
ETH->MACCR |= ETH_Mode_FullDuplex;
|
||||||
|
}
|
||||||
|
else /* half duplex */
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~ETH_Mode_FullDuplex;
|
||||||
|
}
|
||||||
|
|
||||||
|
LinkSta = 1;
|
||||||
|
AccelerateLinkStep = 0;
|
||||||
|
LinkProcessingStep = 0;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
ETH_Start( );
|
||||||
|
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x0 );
|
||||||
|
phy_stat = 0x0;
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x13, phy_stat );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LinkDownCfg
|
||||||
|
*
|
||||||
|
* @brief When the PHY is disconnected, configure the relevant functions.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_LinkDownCfg(void)
|
||||||
|
{
|
||||||
|
LinkSta = 0;
|
||||||
|
LinkVaildFlag = 0;
|
||||||
|
LinkProcessingTime = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_PHYLink
|
||||||
|
*
|
||||||
|
* @brief Configure MAC parameters after the PHY Link is successful.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_PHYLink( void )
|
||||||
|
{
|
||||||
|
u32 phy_stat, phy_anlpar, phy_bcr;
|
||||||
|
uint8_t timeout = 0;
|
||||||
|
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BSR );
|
||||||
|
phy_anlpar = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_ANLPAR);
|
||||||
|
phy_bcr = ETH_ReadPHYRegister( gPHYAddress, PHY_BCR);
|
||||||
|
|
||||||
|
if((ChipId & 0xf0) <= 0x20)
|
||||||
|
{
|
||||||
|
while(phy_stat == 0)
|
||||||
|
{
|
||||||
|
Delay_Us(100);
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, PHY_BSR);
|
||||||
|
if(timeout++ == 15) break;
|
||||||
|
}
|
||||||
|
if(LastPhyStat == phy_stat) return;
|
||||||
|
}
|
||||||
|
LastPhyStat = phy_stat;
|
||||||
|
|
||||||
|
WCHNET_PhyStatus( phy_stat );
|
||||||
|
if(phy_stat & PHY_Linked_Status) //LinkUp
|
||||||
|
{
|
||||||
|
if(phy_bcr & PHY_AutoNegotiation)
|
||||||
|
{
|
||||||
|
if(phy_anlpar == 0)
|
||||||
|
{
|
||||||
|
ETH_LinkUpCfg();
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
if(phy_stat & PHY_AutoNego_Complete)
|
||||||
|
{
|
||||||
|
ETH_LinkUpCfg();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
ETH_LinkUpCfg();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else { //LinkDown
|
||||||
|
/*Link down*/
|
||||||
|
ETH_LinkDownCfg();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_RegInit
|
||||||
|
*
|
||||||
|
* @brief ETH register initialization.
|
||||||
|
*
|
||||||
|
* @param ETH_InitStruct:initialization struct.
|
||||||
|
* PHYAddress:PHY address.
|
||||||
|
*
|
||||||
|
* @return Initialization status.
|
||||||
|
*/
|
||||||
|
uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress )
|
||||||
|
{
|
||||||
|
uint16_t tmpreg;
|
||||||
|
/* Set the SMI interface clock, set as the main frequency divided by 42 */
|
||||||
|
ETH->MACMIIAR = (uint32_t)ETH_MACMIIAR_CR_Div42;
|
||||||
|
|
||||||
|
/*------------------------ MAC register configuration -------------------------------------------*/
|
||||||
|
ETH->MACCR = (uint32_t)(ETH_InitStruct->ETH_Watchdog |
|
||||||
|
ETH_InitStruct->ETH_Jabber |
|
||||||
|
ETH_InitStruct->ETH_InterFrameGap |
|
||||||
|
ETH_InitStruct->ETH_ChecksumOffload |
|
||||||
|
ETH_InitStruct->ETH_AutomaticPadCRCStrip |
|
||||||
|
ETH_InitStruct->ETH_LoopbackMode);
|
||||||
|
|
||||||
|
ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
|
||||||
|
ETH_InitStruct->ETH_SourceAddrFilter |
|
||||||
|
ETH_InitStruct->ETH_PassControlFrames |
|
||||||
|
ETH_InitStruct->ETH_BroadcastFramesReception |
|
||||||
|
ETH_InitStruct->ETH_DestinationAddrFilter |
|
||||||
|
ETH_InitStruct->ETH_PromiscuousMode |
|
||||||
|
ETH_InitStruct->ETH_MulticastFramesFilter |
|
||||||
|
ETH_InitStruct->ETH_UnicastFramesFilter);
|
||||||
|
|
||||||
|
ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
|
||||||
|
ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
|
||||||
|
|
||||||
|
ETH->MACFCR = (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
|
||||||
|
ETH_InitStruct->ETH_UnicastPauseFrameDetect |
|
||||||
|
ETH_InitStruct->ETH_ReceiveFlowControl |
|
||||||
|
ETH_InitStruct->ETH_TransmitFlowControl);
|
||||||
|
|
||||||
|
ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
|
||||||
|
ETH_InitStruct->ETH_VLANTagIdentifier);
|
||||||
|
|
||||||
|
ETH->DMAOMR = (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
|
||||||
|
ETH_InitStruct->ETH_TransmitStoreForward |
|
||||||
|
ETH_InitStruct->ETH_ForwardErrorFrames |
|
||||||
|
ETH_InitStruct->ETH_ForwardUndersizedGoodFrames);
|
||||||
|
|
||||||
|
/* Reset the physical layer */
|
||||||
|
ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset);
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x00 );
|
||||||
|
tmpreg = ETH_ReadPHYRegister(gPHYAddress, 24);
|
||||||
|
if(tmpreg & (1<<1)) ETH_WritePHYRegister(PHYAddress, PHY_BCR, 0x3100);
|
||||||
|
|
||||||
|
/*Reads the default value of the PHY_BSR register*/
|
||||||
|
LastPhyStat = ETH_ReadPHYRegister( PHY_ADDRESS, PHY_BSR );
|
||||||
|
return ETH_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_Configuration
|
||||||
|
*
|
||||||
|
* @brief Ethernet configure.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_Configuration( uint8_t *macAddr )
|
||||||
|
{
|
||||||
|
ETH_InitTypeDef ETH_InitStructure;
|
||||||
|
uint16_t timeout = 10000;
|
||||||
|
|
||||||
|
/* Enable Ethernet MAC clock */
|
||||||
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | \
|
||||||
|
RCC_AHBPeriph_ETH_MAC_Tx | \
|
||||||
|
RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);
|
||||||
|
|
||||||
|
gPHYAddress = PHY_ADDRESS;
|
||||||
|
|
||||||
|
/* Enable MII GPIO */
|
||||||
|
ETH_MIIPinInit( );
|
||||||
|
|
||||||
|
/* Reset ETHERNET on AHB Bus */
|
||||||
|
ETH_DeInit();
|
||||||
|
|
||||||
|
/* Software reset */
|
||||||
|
ETH_SoftwareReset();
|
||||||
|
|
||||||
|
/* Wait for software reset */
|
||||||
|
do{
|
||||||
|
Delay_Us(10);
|
||||||
|
if( !--timeout ) break;
|
||||||
|
}while(ETH->DMABMR & ETH_DMABMR_SR);
|
||||||
|
|
||||||
|
/* ETHERNET Configuration */
|
||||||
|
/*------------------------ MAC -----------------------------------*/
|
||||||
|
ETH_InitStructure.ETH_Watchdog = ETH_Watchdog_Enable;
|
||||||
|
ETH_InitStructure.ETH_Jabber = ETH_Jabber_Enable;
|
||||||
|
ETH_InitStructure.ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
|
||||||
|
#if HARDWARE_CHECKSUM_CONFIG
|
||||||
|
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
|
||||||
|
#else
|
||||||
|
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
|
||||||
|
#endif
|
||||||
|
ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
|
||||||
|
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
|
||||||
|
|
||||||
|
/* Filter function configuration */
|
||||||
|
ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
|
||||||
|
ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
|
||||||
|
ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
|
||||||
|
ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
|
||||||
|
ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
|
||||||
|
ETH_InitStructure.ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
|
||||||
|
ETH_InitStructure.ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
|
||||||
|
ETH_InitStructure.ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
|
||||||
|
|
||||||
|
ETH_InitStructure.ETH_HashTableHigh = 0x0;
|
||||||
|
ETH_InitStructure.ETH_HashTableLow = 0x0;
|
||||||
|
|
||||||
|
/* VLan function configuration */
|
||||||
|
ETH_InitStructure.ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
|
||||||
|
ETH_InitStructure.ETH_VLANTagIdentifier = 0x0;
|
||||||
|
|
||||||
|
/* Flow Control function configuration */
|
||||||
|
ETH_InitStructure.ETH_PauseTime = 0x0;
|
||||||
|
ETH_InitStructure.ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
|
||||||
|
ETH_InitStructure.ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
|
||||||
|
ETH_InitStructure.ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
|
||||||
|
|
||||||
|
/*------------------------ DMA -----------------------------------*/
|
||||||
|
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
||||||
|
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
||||||
|
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
||||||
|
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
||||||
|
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
||||||
|
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable;
|
||||||
|
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable;
|
||||||
|
/* Configure Ethernet */
|
||||||
|
ETH_RegInit( Ð_InitStructure, gPHYAddress );
|
||||||
|
|
||||||
|
/* Configure MAC address */
|
||||||
|
ETH->MACA0HR = (uint32_t)((macAddr[5]<<8) | macAddr[4]);
|
||||||
|
ETH->MACA0LR = (uint32_t)(macAddr[0] | (macAddr[1]<<8) | (macAddr[2]<<16) | (macAddr[3]<<24));
|
||||||
|
|
||||||
|
/* Mask the interrupt that Tx good frame count counter reaches half the maximum value */
|
||||||
|
ETH->MMCTIMR = ETH_MMCTIMR_TGFM;
|
||||||
|
/* Mask the interrupt that Rx good unicast frames counter reaches half the maximum value */
|
||||||
|
/* Mask the interrupt that Rx crc error counter reaches half the maximum value */
|
||||||
|
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM;
|
||||||
|
|
||||||
|
ETH_DMAITConfig(ETH_DMA_IT_NIS |\
|
||||||
|
ETH_DMA_IT_R |\
|
||||||
|
ETH_DMA_IT_T |\
|
||||||
|
ETH_DMA_IT_AIS |\
|
||||||
|
ETH_DMA_IT_RBU,\
|
||||||
|
ENABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_TxPktChainMode
|
||||||
|
*
|
||||||
|
* @brief Ethernet sends data frames in chain mode.
|
||||||
|
*
|
||||||
|
* @param len Send data length
|
||||||
|
* pBuff send buffer pointer
|
||||||
|
*
|
||||||
|
* @return Send status.
|
||||||
|
*/
|
||||||
|
uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff )
|
||||||
|
{
|
||||||
|
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
||||||
|
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
|
||||||
|
{
|
||||||
|
/* Return ERROR: OWN bit set */
|
||||||
|
return ETH_ERROR;
|
||||||
|
}
|
||||||
|
/* Setting the Frame Length: bits[12:0] */
|
||||||
|
DMATxDescToSet->ControlBufferSize = (len & ETH_DMATxDesc_TBS1);
|
||||||
|
DMATxDescToSet->Buffer1Addr = (uint32_t)pBuff;
|
||||||
|
|
||||||
|
/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
|
||||||
|
#if HARDWARE_CHECKSUM_CONFIG
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_CIC_TCPUDPICMP_Full;
|
||||||
|
#else
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
||||||
|
|
||||||
|
/* Clear TBUS ETHERNET DMA flag */
|
||||||
|
ETH->DMASR = ETH_DMASR_TBUS;
|
||||||
|
/* Resume DMA transmission*/
|
||||||
|
ETH->DMATPDR = 0;
|
||||||
|
|
||||||
|
/* Update the ETHERNET DMA global Tx descriptor with next Tx descriptor */
|
||||||
|
/* Chained Mode */
|
||||||
|
/* Selects the next DMA Tx descriptor list for next buffer to send */
|
||||||
|
DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
|
||||||
|
/* Return SUCCESS */
|
||||||
|
return ETH_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_Stop
|
||||||
|
*
|
||||||
|
* @brief Disables ENET MAC and DMA reception/transmission.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_Stop(void)
|
||||||
|
{
|
||||||
|
ETH_MACTransmissionCmd(DISABLE);
|
||||||
|
ETH_FlushTransmitFIFO();
|
||||||
|
ETH_MACReceptionCmd(DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ReInitMACReg
|
||||||
|
*
|
||||||
|
* @brief Reinitialize MAC register.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ReInitMACReg(void)
|
||||||
|
{
|
||||||
|
uint16_t timeout = 10000;
|
||||||
|
uint32_t maccr, macmiiar, macffr, machthr, machtlr;
|
||||||
|
uint32_t macfcr, macvlantr, dmaomr;
|
||||||
|
|
||||||
|
/* Wait for sending data to complete */
|
||||||
|
while((ETH->DMASR & (7 << 20)) != ETH_DMA_TransmitProcess_Suspended);
|
||||||
|
|
||||||
|
ETH_Stop();
|
||||||
|
|
||||||
|
/* Record the register value */
|
||||||
|
macmiiar = ETH->MACMIIAR;
|
||||||
|
maccr = ETH->MACCR;
|
||||||
|
macffr = ETH->MACFFR;
|
||||||
|
machthr = ETH->MACHTHR;
|
||||||
|
machtlr = ETH->MACHTLR;
|
||||||
|
macfcr = ETH->MACFCR;
|
||||||
|
macvlantr = ETH->MACVLANTR;
|
||||||
|
dmaomr = ETH->DMAOMR;
|
||||||
|
|
||||||
|
/* Reset ETHERNET on AHB Bus */
|
||||||
|
ETH_DeInit();
|
||||||
|
|
||||||
|
/* Software reset */
|
||||||
|
ETH_SoftwareReset();
|
||||||
|
|
||||||
|
/* Wait for software reset */
|
||||||
|
do{
|
||||||
|
Delay_Us(10);
|
||||||
|
if( !--timeout ) break;
|
||||||
|
}while(ETH->DMABMR & ETH_DMABMR_SR);
|
||||||
|
|
||||||
|
/* Configure MAC address */
|
||||||
|
ETH->MACA0HR = (uint32_t)((MACAddr[5]<<8) | MACAddr[4]);
|
||||||
|
ETH->MACA0LR = (uint32_t)(MACAddr[0] | (MACAddr[1]<<8) | (MACAddr[2]<<16) | (MACAddr[3]<<24));
|
||||||
|
|
||||||
|
/* Mask the interrupt that Tx good frame count counter reaches half the maximum value */
|
||||||
|
ETH->MMCTIMR = ETH_MMCTIMR_TGFM;
|
||||||
|
/* Mask the interrupt that Rx good unicast frames counter reaches half the maximum value */
|
||||||
|
/* Mask the interrupt that Rx crc error counter reaches half the maximum value */
|
||||||
|
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM;
|
||||||
|
|
||||||
|
ETH_DMAITConfig(ETH_DMA_IT_NIS |\
|
||||||
|
ETH_DMA_IT_R |\
|
||||||
|
ETH_DMA_IT_T |\
|
||||||
|
ETH_DMA_IT_AIS |\
|
||||||
|
ETH_DMA_IT_RBU,\
|
||||||
|
ENABLE);
|
||||||
|
|
||||||
|
ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB);
|
||||||
|
ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB);
|
||||||
|
pDMARxSet = DMARxDscrTab;
|
||||||
|
pDMATxSet = DMATxDscrTab;
|
||||||
|
|
||||||
|
ETH->MACMIIAR = macmiiar;
|
||||||
|
ETH->MACCR = maccr;
|
||||||
|
ETH->MACFFR = macffr;
|
||||||
|
ETH->MACHTHR = machthr;
|
||||||
|
ETH->MACHTLR = machtlr;
|
||||||
|
ETH->MACFCR = macfcr;
|
||||||
|
ETH->MACVLANTR = macvlantr;
|
||||||
|
ETH->DMAOMR = dmaomr;
|
||||||
|
|
||||||
|
ETH_Start( );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_RecProcess
|
||||||
|
*
|
||||||
|
* @brief Receiving related processing
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_RecProcess(void)
|
||||||
|
{
|
||||||
|
if(((ChipId & 0xf0) <= 0x20) && \
|
||||||
|
((ETH->DMAMFBOCR & 0x1FFE0000) != 0))
|
||||||
|
{
|
||||||
|
ReInitMACReg();
|
||||||
|
/* Resume DMA transport */
|
||||||
|
ETH->DMARPDR = 0;
|
||||||
|
ETH->DMATPDR = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_ETHIsr
|
||||||
|
*
|
||||||
|
* @brief Ethernet Interrupt Service Routine
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WCHNET_ETHIsr(void)
|
||||||
|
{
|
||||||
|
uint32_t int_sta;
|
||||||
|
|
||||||
|
int_sta = ETH->DMASR;
|
||||||
|
if (int_sta & ETH_DMA_IT_AIS)
|
||||||
|
{
|
||||||
|
if (int_sta & ETH_DMA_IT_RBU)
|
||||||
|
{
|
||||||
|
WCHNET_RecProcess();
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_RBU);
|
||||||
|
}
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_AIS);
|
||||||
|
}
|
||||||
|
|
||||||
|
if( int_sta & ETH_DMA_IT_NIS )
|
||||||
|
{
|
||||||
|
if( int_sta & ETH_DMA_IT_R )
|
||||||
|
{
|
||||||
|
/*If you don't use the Ethernet library,
|
||||||
|
* you can do some data processing operations here*/
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
|
||||||
|
}
|
||||||
|
if( int_sta & ETH_DMA_IT_T )
|
||||||
|
{
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
|
||||||
|
}
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_Init
|
||||||
|
*
|
||||||
|
* @brief Ethernet initialization.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_Init( uint8_t *macAddr )
|
||||||
|
{
|
||||||
|
ChipId = DBGMCU_GetCHIPID();
|
||||||
|
ETH_Configuration( macAddr );
|
||||||
|
ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB);
|
||||||
|
ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB);
|
||||||
|
pDMARxSet = DMARxDscrTab;
|
||||||
|
pDMATxSet = DMATxDscrTab;
|
||||||
|
NVIC_EnableIRQ(ETH_IRQn);
|
||||||
|
NVIC_SetPriority(ETH_IRQn, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LibInit
|
||||||
|
*
|
||||||
|
* @brief Ethernet library initialization program
|
||||||
|
*
|
||||||
|
* @return command status
|
||||||
|
*/
|
||||||
|
uint8_t ETH_LibInit( uint8_t *ip, uint8_t *gwip, uint8_t *mask, uint8_t *macaddr )
|
||||||
|
{
|
||||||
|
uint8_t s;
|
||||||
|
struct _WCH_CFG cfg;
|
||||||
|
|
||||||
|
memset(&cfg,0,sizeof(cfg));
|
||||||
|
cfg.TxBufSize = ETH_TX_BUF_SZE;
|
||||||
|
cfg.TCPMss = WCHNET_TCP_MSS;
|
||||||
|
cfg.HeapSize = WCHNET_MEM_HEAP_SIZE;
|
||||||
|
cfg.ARPTableNum = WCHNET_NUM_ARP_TABLE;
|
||||||
|
cfg.MiscConfig0 = WCHNET_MISC_CONFIG0;
|
||||||
|
cfg.MiscConfig1 = WCHNET_MISC_CONFIG1;
|
||||||
|
cfg.net_send = ETH_TxPktChainMode;
|
||||||
|
cfg.CheckValid = WCHNET_CFG_VALID;
|
||||||
|
s = WCHNET_ConfigLIB(&cfg);
|
||||||
|
if( s ){
|
||||||
|
return (s);
|
||||||
|
}
|
||||||
|
s = WCHNET_Init(ip,gwip,mask,macaddr);
|
||||||
|
ETH_Init( macaddr );
|
||||||
|
return (s);
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************** endfile @ eth_driver ******************************/
|
||||||
@@ -0,0 +1,714 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : eth_driver.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.3.0
|
||||||
|
* Date : 2022/06/02
|
||||||
|
* Description : eth program body.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#include "string.h"
|
||||||
|
#include "eth_driver.h"
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB]; /* MAC receive descriptor, 4-byte aligned*/
|
||||||
|
__attribute__((__aligned__(4))) ETH_DMADESCTypeDef DMATxDscrTab[ETH_TXBUFNB]; /* MAC send descriptor, 4-byte aligned */
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) uint8_t MACRxBuf[ETH_RXBUFNB*ETH_RX_BUF_SZE]; /* MAC receive buffer, 4-byte aligned */
|
||||||
|
__attribute__((__aligned__(4))) uint8_t MACTxBuf[ETH_TXBUFNB*ETH_TX_BUF_SZE]; /* MAC send buffer, 4-byte aligned */
|
||||||
|
|
||||||
|
__attribute__((__aligned__(4))) SOCK_INF SocketInf[WCHNET_MAX_SOCKET_NUM]; /* Socket information table, 4-byte alignment */
|
||||||
|
const uint16_t MemNum[8] = {WCHNET_NUM_IPRAW,
|
||||||
|
WCHNET_NUM_UDP,
|
||||||
|
WCHNET_NUM_TCP,
|
||||||
|
WCHNET_NUM_TCP_LISTEN,
|
||||||
|
WCHNET_NUM_TCP_SEG,
|
||||||
|
WCHNET_NUM_IP_REASSDATA,
|
||||||
|
WCHNET_NUM_PBUF,
|
||||||
|
WCHNET_NUM_POOL_BUF
|
||||||
|
};
|
||||||
|
const uint16_t MemSize[8] = {WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IPRAW_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_UDP_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB_LISTEN),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_SEG),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IP_REASSDATA),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF),
|
||||||
|
WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF) + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_POOL_BUF)
|
||||||
|
};
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Memp_Memory[WCHNET_MEMP_SIZE];
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Mem_Heap_Memory[WCHNET_RAM_HEAP_SIZE];
|
||||||
|
__attribute__((__aligned__(4)))uint8_t Mem_ArpTable[WCHNET_RAM_ARP_TABLE_SIZE];
|
||||||
|
|
||||||
|
uint16_t gPHYAddress;
|
||||||
|
uint32_t volatile LocalTime;
|
||||||
|
|
||||||
|
ETH_DMADESCTypeDef *pDMARxSet;
|
||||||
|
ETH_DMADESCTypeDef *pDMATxSet;
|
||||||
|
|
||||||
|
u32 ChipId = 0;
|
||||||
|
#if !LINK_STAT_ACQUISITION_METHOD
|
||||||
|
u16 LastPhyStat = 0;
|
||||||
|
u32 LastQueryPhyTime = 0;
|
||||||
|
#endif
|
||||||
|
extern u8 MACAddr[6];
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_GetMacAddr
|
||||||
|
*
|
||||||
|
* @brief Get the MAC address
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_GetMacAddr( uint8_t *p )
|
||||||
|
{
|
||||||
|
uint8_t i;
|
||||||
|
uint8_t *macaddr = (uint8_t *)(ROM_CFG_USERADR_ID+5);
|
||||||
|
|
||||||
|
for(i=0;i<6;i++)
|
||||||
|
{
|
||||||
|
*p = *macaddr;
|
||||||
|
p++;
|
||||||
|
macaddr--;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_TimeIsr
|
||||||
|
*
|
||||||
|
* @brief
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_TimeIsr( uint16_t timperiod )
|
||||||
|
{
|
||||||
|
LocalTime += timperiod;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_QueryPhySta
|
||||||
|
*
|
||||||
|
* @brief Query external PHY status
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
#if !LINK_STAT_ACQUISITION_METHOD
|
||||||
|
void WCHNET_QueryPhySta(void)
|
||||||
|
{
|
||||||
|
u16 phy_stat;
|
||||||
|
if(QUERY_STAT_FLAG){ /* Query the PHY link status every 1s */
|
||||||
|
LastQueryPhyTime = LocalTime / 1000;
|
||||||
|
ETH_WritePHYRegister( PHY_ADDRESS, 0x1F, 0x0a43 );
|
||||||
|
/*In some cases the status is not updated in time,
|
||||||
|
* so read this register twice to get the correct status value.*/
|
||||||
|
ETH_ReadPHYRegister( PHY_ADDRESS, 0x1A);
|
||||||
|
phy_stat = ETH_ReadPHYRegister( PHY_ADDRESS, 0x1A) & 0x04;
|
||||||
|
if((phy_stat != LastPhyStat) && (phy_stat != 0xffff)){
|
||||||
|
ETH_PHYLink();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_MainTask
|
||||||
|
*
|
||||||
|
* @brief library main task function
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_MainTask(void)
|
||||||
|
{
|
||||||
|
WCHNET_NetInput( ); /* Ethernet data input */
|
||||||
|
WCHNET_PeriodicHandle( ); /* Protocol stack time-related task processing */
|
||||||
|
|
||||||
|
#if !LINK_STAT_ACQUISITION_METHOD
|
||||||
|
WCHNET_QueryPhySta(); /* Query external PHY status */
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_RGMIIPinInit
|
||||||
|
*
|
||||||
|
* @brief PHY RGMII interface GPIO initialization.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_RGMIIPinInit(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);
|
||||||
|
GPIOB->CFGHR &= ~(0xff<<16);
|
||||||
|
GPIOB->CFGHR |= (0xbb<<16);
|
||||||
|
GPIOB->CFGLR &= ~(0xff<<4);
|
||||||
|
|
||||||
|
GPIO_Output(GPIOA, GPIO_Pin_2);
|
||||||
|
GPIO_Output(GPIOA, GPIO_Pin_3);
|
||||||
|
GPIO_Output(GPIOA, GPIO_Pin_7);
|
||||||
|
GPIO_Output(GPIOC, GPIO_Pin_4);
|
||||||
|
GPIO_Output(GPIOC, GPIO_Pin_5);
|
||||||
|
GPIO_Output(GPIOB, GPIO_Pin_0);
|
||||||
|
|
||||||
|
GPIO_Input(GPIOC, GPIO_Pin_0);
|
||||||
|
GPIO_Input(GPIOC, GPIO_Pin_1);
|
||||||
|
GPIO_Input(GPIOC, GPIO_Pin_2);
|
||||||
|
GPIO_Input(GPIOC, GPIO_Pin_3);
|
||||||
|
GPIO_Input(GPIOA, GPIO_Pin_0);
|
||||||
|
GPIO_Input(GPIOA, GPIO_Pin_1);
|
||||||
|
|
||||||
|
GPIO_Input(GPIOB, GPIO_Pin_1); /* 125m in */
|
||||||
|
GPIO_Input(GPIOC, GPIO_Pin_7); /* interrupt pin */
|
||||||
|
}
|
||||||
|
|
||||||
|
#if LINK_STAT_ACQUISITION_METHOD
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_Line_Init
|
||||||
|
*
|
||||||
|
* @brief Configure EXTI Line7.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void EXTI_Line_Init(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||||
|
EXTI_InitTypeDef EXTI_InitStructure = {0};
|
||||||
|
NVIC_InitTypeDef NVIC_InitStructure = {0};
|
||||||
|
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOC, ENABLE);
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
/* GPIOC 7 ----> EXTI_Line7 */
|
||||||
|
GPIO_EXTILineConfig(GPIO_PortSourceGPIOC, GPIO_PinSource7);
|
||||||
|
EXTI_InitStructure.EXTI_Line = EXTI_Line7;
|
||||||
|
EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
|
||||||
|
EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
|
||||||
|
EXTI_InitStructure.EXTI_LineCmd = ENABLE;
|
||||||
|
EXTI_Init(&EXTI_InitStructure);
|
||||||
|
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannel = EXTI9_5_IRQn;
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2;
|
||||||
|
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||||
|
NVIC_Init(&NVIC_InitStructure);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PHY_InterruptInit
|
||||||
|
*
|
||||||
|
* @brief Configure PHY interrupt function,Supported chip is:RTL8211FS
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void PHY_InterruptInit(void)
|
||||||
|
{
|
||||||
|
uint16_t RegValue;
|
||||||
|
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x1F, 0x0a42 );
|
||||||
|
RegValue = ETH_ReadPHYRegister(gPHYAddress, 0x12);
|
||||||
|
/* enable Link Status Change Interrupt and
|
||||||
|
* Auto-Negotiation Completed Interrupt*/
|
||||||
|
RegValue |= (1<<4)|(1<<3);
|
||||||
|
ETH_WritePHYRegister(gPHYAddress, 0x12, RegValue );
|
||||||
|
/* Clear the Interrupt status */
|
||||||
|
ETH_WritePHYRegister( gPHYAddress, 0x1F, 0x0a43 );
|
||||||
|
ETH_ReadPHYRegister( gPHYAddress, 0x1D);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_PHYLink
|
||||||
|
*
|
||||||
|
* @brief Configure MAC parameters after the PHY Link is successful.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ETH_PHYLink( void )
|
||||||
|
{
|
||||||
|
u32 phy_stat;
|
||||||
|
#if !LINK_STAT_ACQUISITION_METHOD
|
||||||
|
uint8_t timeout = 0;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
ETH_WritePHYRegister( gPHYAddress, 0x1F, 0x0a43 );
|
||||||
|
/*In some cases the status is not updated in time,
|
||||||
|
* so read this register twice to get the correct status value.*/
|
||||||
|
ETH_ReadPHYRegister( gPHYAddress, 0x1A);
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x1A);
|
||||||
|
#if !LINK_STAT_ACQUISITION_METHOD
|
||||||
|
if((ChipId & 0xf0) <= 0x20)
|
||||||
|
{
|
||||||
|
while(phy_stat == 0)
|
||||||
|
{
|
||||||
|
Delay_Us(100);
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x1A);
|
||||||
|
if(timeout++ == 15) break;
|
||||||
|
}
|
||||||
|
if(LastPhyStat == (phy_stat & 0x04)) return;
|
||||||
|
}
|
||||||
|
LastPhyStat = phy_stat & 0x04;
|
||||||
|
#endif
|
||||||
|
WCHNET_PhyStatus( phy_stat );
|
||||||
|
|
||||||
|
if( phy_stat & 0x04 )
|
||||||
|
{
|
||||||
|
/* Configure the polarity and delay of TXC */
|
||||||
|
RGMII_TXC_Delay(0, 4);
|
||||||
|
if( phy_stat & 0x08 )
|
||||||
|
{
|
||||||
|
ETH->MACCR |= ETH_Mode_FullDuplex;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~ETH_Mode_FullDuplex;
|
||||||
|
}
|
||||||
|
if( (phy_stat & 0x30) == 0x00 )
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M);
|
||||||
|
}
|
||||||
|
else if( (phy_stat & 0x30) == 0x10 )
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M);
|
||||||
|
ETH->MACCR |= ETH_Speed_100M;
|
||||||
|
}
|
||||||
|
else if( (phy_stat & 0x30) == 0x20 )
|
||||||
|
{
|
||||||
|
ETH->MACCR &= ~(ETH_Speed_100M|ETH_Speed_1000M);
|
||||||
|
ETH->MACCR |= ETH_Speed_1000M;
|
||||||
|
/* Configure the polarity and delay of TXC */
|
||||||
|
if((ChipId & 0xf0) >= 0x60)
|
||||||
|
RGMII_TXC_Delay(1, 2);
|
||||||
|
}
|
||||||
|
ETH_Start( );
|
||||||
|
}
|
||||||
|
phy_stat = ETH_ReadPHYRegister( gPHYAddress, 0x1D); /* Clear the Interrupt status */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_RegInit
|
||||||
|
*
|
||||||
|
* @brief ETH register initialization.
|
||||||
|
*
|
||||||
|
* @param ETH_InitStruct:initialization struct.
|
||||||
|
* PHYAddress:PHY address.
|
||||||
|
*
|
||||||
|
* @return Initialization status.
|
||||||
|
*/
|
||||||
|
uint32_t ETH_RegInit( ETH_InitTypeDef* ETH_InitStruct, uint16_t PHYAddress )
|
||||||
|
{
|
||||||
|
/* Set the SMI interface clock, set as the main frequency divided by 42 */
|
||||||
|
ETH->MACMIIAR = (uint32_t)ETH_MACMIIAR_CR_Div42;
|
||||||
|
|
||||||
|
/*------------------------ MAC register configuration -------------------------------------------*/
|
||||||
|
ETH->MACCR = (uint32_t)(ETH_InitStruct->ETH_Watchdog |
|
||||||
|
ETH_InitStruct->ETH_Jabber |
|
||||||
|
ETH_InitStruct->ETH_InterFrameGap |
|
||||||
|
ETH_InitStruct->ETH_ChecksumOffload |
|
||||||
|
ETH_InitStruct->ETH_AutomaticPadCRCStrip |
|
||||||
|
ETH_InitStruct->ETH_LoopbackMode);
|
||||||
|
|
||||||
|
ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll |
|
||||||
|
ETH_InitStruct->ETH_SourceAddrFilter |
|
||||||
|
ETH_InitStruct->ETH_PassControlFrames |
|
||||||
|
ETH_InitStruct->ETH_BroadcastFramesReception |
|
||||||
|
ETH_InitStruct->ETH_DestinationAddrFilter |
|
||||||
|
ETH_InitStruct->ETH_PromiscuousMode |
|
||||||
|
ETH_InitStruct->ETH_MulticastFramesFilter |
|
||||||
|
ETH_InitStruct->ETH_UnicastFramesFilter);
|
||||||
|
|
||||||
|
ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh;
|
||||||
|
ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow;
|
||||||
|
|
||||||
|
ETH->MACFCR = (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) |
|
||||||
|
ETH_InitStruct->ETH_UnicastPauseFrameDetect |
|
||||||
|
ETH_InitStruct->ETH_ReceiveFlowControl |
|
||||||
|
ETH_InitStruct->ETH_TransmitFlowControl);
|
||||||
|
|
||||||
|
ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison |
|
||||||
|
ETH_InitStruct->ETH_VLANTagIdentifier);
|
||||||
|
|
||||||
|
ETH->DMAOMR = (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame |
|
||||||
|
ETH_InitStruct->ETH_TransmitStoreForward |
|
||||||
|
ETH_InitStruct->ETH_ForwardErrorFrames |
|
||||||
|
ETH_InitStruct->ETH_ForwardUndersizedGoodFrames);
|
||||||
|
|
||||||
|
/* Reset the physical layer */
|
||||||
|
ETH_WritePHYRegister(PHYAddress, PHY_BCR, PHY_Reset);
|
||||||
|
return ETH_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_Configuration
|
||||||
|
*
|
||||||
|
* @brief Ethernet configure.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_Configuration( uint8_t *macAddr )
|
||||||
|
{
|
||||||
|
ETH_InitTypeDef ETH_InitStructure;
|
||||||
|
uint16_t timeout = 10000;
|
||||||
|
|
||||||
|
/* Enable Ethernet MAC clock */
|
||||||
|
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC | \
|
||||||
|
RCC_AHBPeriph_ETH_MAC_Tx | \
|
||||||
|
RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);
|
||||||
|
|
||||||
|
gPHYAddress = PHY_ADDRESS;
|
||||||
|
|
||||||
|
/* Enable 1G MAC*/
|
||||||
|
EXTEN->EXTEN_CTR |= EXTEN_ETH_RGMII_SEL;
|
||||||
|
RCC_ETH1GCLKConfig(RCC_ETH1GCLKSource_PB1_IN);
|
||||||
|
RCC_ETH1G_125Mcmd(ENABLE);
|
||||||
|
/* Enable RGMII GPIO */
|
||||||
|
ETH_RGMIIPinInit();
|
||||||
|
|
||||||
|
/* Reset ETHERNET on AHB Bus */
|
||||||
|
ETH_DeInit();
|
||||||
|
|
||||||
|
/* Software reset */
|
||||||
|
ETH_SoftwareReset();
|
||||||
|
|
||||||
|
/* Wait for software reset */
|
||||||
|
do{
|
||||||
|
Delay_Us(10);
|
||||||
|
if( !--timeout ) break;
|
||||||
|
}while(ETH->DMABMR & ETH_DMABMR_SR);
|
||||||
|
|
||||||
|
/* ETHERNET Configuration */
|
||||||
|
/*------------------------ MAC -----------------------------------*/
|
||||||
|
ETH_InitStructure.ETH_Watchdog = ETH_Watchdog_Enable;
|
||||||
|
ETH_InitStructure.ETH_Jabber = ETH_Jabber_Enable;
|
||||||
|
ETH_InitStructure.ETH_InterFrameGap = ETH_InterFrameGap_96Bit;
|
||||||
|
#if HARDWARE_CHECKSUM_CONFIG
|
||||||
|
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
|
||||||
|
#else
|
||||||
|
ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Disable;
|
||||||
|
#endif
|
||||||
|
ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;
|
||||||
|
ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;
|
||||||
|
|
||||||
|
/* Filter function configuration */
|
||||||
|
ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;
|
||||||
|
ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;
|
||||||
|
ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;
|
||||||
|
ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;
|
||||||
|
ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;
|
||||||
|
ETH_InitStructure.ETH_PassControlFrames = ETH_PassControlFrames_BlockAll;
|
||||||
|
ETH_InitStructure.ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal;
|
||||||
|
ETH_InitStructure.ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable;
|
||||||
|
|
||||||
|
ETH_InitStructure.ETH_HashTableHigh = 0x0;
|
||||||
|
ETH_InitStructure.ETH_HashTableLow = 0x0;
|
||||||
|
|
||||||
|
/* VLan function configuration */
|
||||||
|
ETH_InitStructure.ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit;
|
||||||
|
ETH_InitStructure.ETH_VLANTagIdentifier = 0x0;
|
||||||
|
|
||||||
|
/* Flow Control function configuration */
|
||||||
|
ETH_InitStructure.ETH_PauseTime = 0x0;
|
||||||
|
ETH_InitStructure.ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable;
|
||||||
|
ETH_InitStructure.ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable;
|
||||||
|
ETH_InitStructure.ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable;
|
||||||
|
|
||||||
|
/*------------------------ DMA -----------------------------------*/
|
||||||
|
/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
|
||||||
|
the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
|
||||||
|
if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
|
||||||
|
ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;
|
||||||
|
ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
|
||||||
|
ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Enable;
|
||||||
|
ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Enable;
|
||||||
|
/* Configure Ethernet */
|
||||||
|
ETH_RegInit( Ð_InitStructure, gPHYAddress );
|
||||||
|
|
||||||
|
/* Configure MAC address */
|
||||||
|
ETH->MACA0HR = (uint32_t)((macAddr[5]<<8) | macAddr[4]);
|
||||||
|
ETH->MACA0LR = (uint32_t)(macAddr[0] | (macAddr[1]<<8) | (macAddr[2]<<16) | (macAddr[3]<<24));
|
||||||
|
|
||||||
|
/* Mask the interrupt that Tx good frame count counter reaches half the maximum value */
|
||||||
|
ETH->MMCTIMR = ETH_MMCTIMR_TGFM;
|
||||||
|
/* Mask the interrupt that Rx good unicast frames counter reaches half the maximum value */
|
||||||
|
/* Mask the interrupt that Rx crc error counter reaches half the maximum value */
|
||||||
|
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM;
|
||||||
|
|
||||||
|
ETH_DMAITConfig(ETH_DMA_IT_NIS |\
|
||||||
|
ETH_DMA_IT_R |\
|
||||||
|
ETH_DMA_IT_T |\
|
||||||
|
ETH_DMA_IT_AIS |\
|
||||||
|
ETH_DMA_IT_RBU,\
|
||||||
|
ENABLE);
|
||||||
|
|
||||||
|
#if LINK_STAT_ACQUISITION_METHOD
|
||||||
|
/* Configure the PHY interrupt function, the supported chip is: RTL8211FS */
|
||||||
|
PHY_InterruptInit( );
|
||||||
|
/* Configure EXTI Line7. */
|
||||||
|
EXTI_Line_Init( );
|
||||||
|
#else
|
||||||
|
ETH_WritePHYRegister( PHY_ADDRESS, 0x1F, 0x0a43 );
|
||||||
|
/*In some cases the status is not updated in time,
|
||||||
|
* so read this register twice to get the correct status value.*/
|
||||||
|
ETH_ReadPHYRegister( PHY_ADDRESS, 0x1A);
|
||||||
|
LastPhyStat = ETH_ReadPHYRegister( PHY_ADDRESS, 0x1A) & 0x04;
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_TxPktChainMode
|
||||||
|
*
|
||||||
|
* @brief Ethernet sends data frames in chain mode.
|
||||||
|
*
|
||||||
|
* @param len Send data length
|
||||||
|
* pBuff send buffer pointer
|
||||||
|
*
|
||||||
|
* @return Send status.
|
||||||
|
*/
|
||||||
|
uint32_t ETH_TxPktChainMode(uint16_t len, uint32_t *pBuff )
|
||||||
|
{
|
||||||
|
/* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
|
||||||
|
if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (u32)RESET)
|
||||||
|
{
|
||||||
|
/* Return ERROR: OWN bit set */
|
||||||
|
return ETH_ERROR;
|
||||||
|
}
|
||||||
|
/* Setting the Frame Length: bits[12:0] */
|
||||||
|
DMATxDescToSet->ControlBufferSize = (len & ETH_DMATxDesc_TBS1);
|
||||||
|
DMATxDescToSet->Buffer1Addr = (uint32_t)pBuff;
|
||||||
|
|
||||||
|
/* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */
|
||||||
|
#if HARDWARE_CHECKSUM_CONFIG
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS | ETH_DMATxDesc_CIC_TCPUDPICMP_Full;
|
||||||
|
#else
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
|
||||||
|
DMATxDescToSet->Status |= ETH_DMATxDesc_OWN;
|
||||||
|
|
||||||
|
/* Clear TBUS ETHERNET DMA flag */
|
||||||
|
ETH->DMASR = ETH_DMASR_TBUS;
|
||||||
|
/* Resume DMA transmission*/
|
||||||
|
ETH->DMATPDR = 0;
|
||||||
|
|
||||||
|
/* Update the ETHERNET DMA global Tx descriptor with next Tx descriptor */
|
||||||
|
/* Chained Mode */
|
||||||
|
/* Selects the next DMA Tx descriptor list for next buffer to send */
|
||||||
|
DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr);
|
||||||
|
/* Return SUCCESS */
|
||||||
|
return ETH_SUCCESS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_Stop
|
||||||
|
*
|
||||||
|
* @brief Disables ENET MAC and DMA reception/transmission.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_Stop(void)
|
||||||
|
{
|
||||||
|
ETH_MACTransmissionCmd(DISABLE);
|
||||||
|
ETH_FlushTransmitFIFO();
|
||||||
|
ETH_MACReceptionCmd(DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ReInitMACReg
|
||||||
|
*
|
||||||
|
* @brief Reinitialize MAC register.
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void ReInitMACReg(void)
|
||||||
|
{
|
||||||
|
uint16_t timeout = 10000;
|
||||||
|
uint32_t maccr, macmiiar, macffr, machthr, machtlr;
|
||||||
|
uint32_t macfcr, macvlantr, dmaomr;
|
||||||
|
|
||||||
|
/* Wait for sending data to complete */
|
||||||
|
while((ETH->DMASR & (7 << 20)) != ETH_DMA_TransmitProcess_Suspended);
|
||||||
|
|
||||||
|
ETH_Stop();
|
||||||
|
|
||||||
|
/* Record the register value */
|
||||||
|
macmiiar = ETH->MACMIIAR;
|
||||||
|
maccr = ETH->MACCR;
|
||||||
|
macffr = ETH->MACFFR;
|
||||||
|
machthr = ETH->MACHTHR;
|
||||||
|
machtlr = ETH->MACHTLR;
|
||||||
|
macfcr = ETH->MACFCR;
|
||||||
|
macvlantr = ETH->MACVLANTR;
|
||||||
|
dmaomr = ETH->DMAOMR;
|
||||||
|
|
||||||
|
/* Reset ETHERNET on AHB Bus */
|
||||||
|
ETH_DeInit();
|
||||||
|
|
||||||
|
/* Software reset */
|
||||||
|
ETH_SoftwareReset();
|
||||||
|
|
||||||
|
/* Wait for software reset */
|
||||||
|
do{
|
||||||
|
Delay_Us(10);
|
||||||
|
if( !--timeout ) break;
|
||||||
|
}while(ETH->DMABMR & ETH_DMABMR_SR);
|
||||||
|
|
||||||
|
/* Configure MAC address */
|
||||||
|
ETH->MACA0HR = (uint32_t)((MACAddr[5]<<8) | MACAddr[4]);
|
||||||
|
ETH->MACA0LR = (uint32_t)(MACAddr[0] | (MACAddr[1]<<8) | (MACAddr[2]<<16) | (MACAddr[3]<<24));
|
||||||
|
|
||||||
|
/* Mask the interrupt that Tx good frame count counter reaches half the maximum value */
|
||||||
|
ETH->MMCTIMR = ETH_MMCTIMR_TGFM;
|
||||||
|
/* Mask the interrupt that Rx good unicast frames counter reaches half the maximum value */
|
||||||
|
/* Mask the interrupt that Rx crc error counter reaches half the maximum value */
|
||||||
|
ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFCEM;
|
||||||
|
|
||||||
|
ETH_DMAITConfig(ETH_DMA_IT_NIS |\
|
||||||
|
ETH_DMA_IT_R |\
|
||||||
|
ETH_DMA_IT_T |\
|
||||||
|
ETH_DMA_IT_AIS |\
|
||||||
|
ETH_DMA_IT_RBU,\
|
||||||
|
ENABLE);
|
||||||
|
|
||||||
|
ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB);
|
||||||
|
ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB);
|
||||||
|
pDMARxSet = DMARxDscrTab;
|
||||||
|
pDMATxSet = DMATxDscrTab;
|
||||||
|
|
||||||
|
ETH->MACMIIAR = macmiiar;
|
||||||
|
ETH->MACCR = maccr;
|
||||||
|
ETH->MACFFR = macffr;
|
||||||
|
ETH->MACHTHR = machthr;
|
||||||
|
ETH->MACHTLR = machtlr;
|
||||||
|
ETH->MACFCR = macfcr;
|
||||||
|
ETH->MACVLANTR = macvlantr;
|
||||||
|
ETH->DMAOMR = dmaomr;
|
||||||
|
|
||||||
|
ETH_Start( );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_RecProcess
|
||||||
|
*
|
||||||
|
* @brief Receiving related processing
|
||||||
|
*
|
||||||
|
* @param none.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void WCHNET_RecProcess(void)
|
||||||
|
{
|
||||||
|
if(((ChipId & 0xf0) <= 0x20) && \
|
||||||
|
((ETH->DMAMFBOCR & 0x1FFE0000) != 0))
|
||||||
|
{
|
||||||
|
ReInitMACReg();
|
||||||
|
/* Resume DMA transport */
|
||||||
|
ETH->DMARPDR = 0;
|
||||||
|
ETH->DMATPDR = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WCHNET_ETHIsr
|
||||||
|
*
|
||||||
|
* @brief Ethernet Interrupt Service Routine
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WCHNET_ETHIsr(void)
|
||||||
|
{
|
||||||
|
uint32_t int_sta;
|
||||||
|
|
||||||
|
int_sta = ETH->DMASR;
|
||||||
|
if (int_sta & ETH_DMA_IT_AIS)
|
||||||
|
{
|
||||||
|
if (int_sta & ETH_DMA_IT_RBU)
|
||||||
|
{
|
||||||
|
WCHNET_RecProcess();
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_RBU);
|
||||||
|
}
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_AIS);
|
||||||
|
}
|
||||||
|
|
||||||
|
if( int_sta & ETH_DMA_IT_NIS )
|
||||||
|
{
|
||||||
|
if( int_sta & ETH_DMA_IT_R )
|
||||||
|
{
|
||||||
|
/*If you don't use the Ethernet library,
|
||||||
|
* you can do some data processing operations here*/
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_R);
|
||||||
|
}
|
||||||
|
if( int_sta & ETH_DMA_IT_T )
|
||||||
|
{
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_T);
|
||||||
|
}
|
||||||
|
ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_Init
|
||||||
|
*
|
||||||
|
* @brief Ethernet initialization.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_Init( uint8_t *macAddr )
|
||||||
|
{
|
||||||
|
ChipId = DBGMCU_GetCHIPID();
|
||||||
|
ETH_Configuration( macAddr );
|
||||||
|
ETH_DMATxDescChainInit(DMATxDscrTab, MACTxBuf, ETH_TXBUFNB);
|
||||||
|
ETH_DMARxDescChainInit(DMARxDscrTab, MACRxBuf, ETH_RXBUFNB);
|
||||||
|
pDMARxSet = DMARxDscrTab;
|
||||||
|
pDMATxSet = DMATxDscrTab;
|
||||||
|
NVIC_EnableIRQ(ETH_IRQn);
|
||||||
|
NVIC_SetPriority(ETH_IRQn, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_LibInit
|
||||||
|
*
|
||||||
|
* @brief Ethernet library initialization program
|
||||||
|
*
|
||||||
|
* @return command status
|
||||||
|
*/
|
||||||
|
uint8_t ETH_LibInit( uint8_t *ip, uint8_t *gwip, uint8_t *mask, uint8_t *macaddr )
|
||||||
|
{
|
||||||
|
uint8_t s;
|
||||||
|
struct _WCH_CFG cfg;
|
||||||
|
|
||||||
|
memset(&cfg,0,sizeof(cfg));
|
||||||
|
cfg.TxBufSize = ETH_TX_BUF_SZE;
|
||||||
|
cfg.TCPMss = WCHNET_TCP_MSS;
|
||||||
|
cfg.HeapSize = WCHNET_MEM_HEAP_SIZE;
|
||||||
|
cfg.ARPTableNum = WCHNET_NUM_ARP_TABLE;
|
||||||
|
cfg.MiscConfig0 = WCHNET_MISC_CONFIG0;
|
||||||
|
cfg.MiscConfig1 = WCHNET_MISC_CONFIG1;
|
||||||
|
cfg.net_send = ETH_TxPktChainMode;
|
||||||
|
cfg.CheckValid = WCHNET_CFG_VALID;
|
||||||
|
s = WCHNET_ConfigLIB(&cfg);
|
||||||
|
if( s ){
|
||||||
|
return (s);
|
||||||
|
}
|
||||||
|
s = WCHNET_Init(ip,gwip,mask,macaddr);
|
||||||
|
ETH_Init( macaddr );
|
||||||
|
return (s);
|
||||||
|
}
|
||||||
|
|
||||||
|
/******************************** endfile @ eth_driver ******************************/
|
||||||
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
@@ -0,0 +1,630 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : wchnet.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.90
|
||||||
|
* Date : 2023/05/12
|
||||||
|
* Description : This file contains the headers of
|
||||||
|
* the Ethernet protocol stack library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __WCHNET_H__
|
||||||
|
#define __WCHNET_H__
|
||||||
|
|
||||||
|
#include "stdint.h"
|
||||||
|
#ifndef NET_LIB
|
||||||
|
#include "net_config.h"
|
||||||
|
#endif
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define WCHNET_LIB_VER 0x1B //the library version number
|
||||||
|
#define WCHNET_CFG_VALID 0x12345678 //Configuration value valid flag
|
||||||
|
|
||||||
|
/* LED state @LED_STAT */
|
||||||
|
#define LED_ON 0
|
||||||
|
#define LED_OFF 1
|
||||||
|
|
||||||
|
/* PHY state @PHY_STAT */
|
||||||
|
#define PHY_LINK_SUCCESS (1 << 2) //PHY connection success
|
||||||
|
#define PHY_AUTO_SUCCESS (1 << 5) //PHY auto negotiation completed
|
||||||
|
|
||||||
|
/* Library initialization state @CFG_INIT_STAT */
|
||||||
|
#define INIT_OK 0x00
|
||||||
|
#define INIT_ERR_RX_BUF_SIZE 0x01
|
||||||
|
#define INIT_ERR_TCP_MSS 0x02
|
||||||
|
#define INIT_ERR_HEAP_SIZE 0x03
|
||||||
|
#define INIT_ERR_ARP_TABLE_NEM 0x04
|
||||||
|
#define INIT_ERR_MISC_CONFIG0 0x05
|
||||||
|
#define INIT_ERR_MISC_CONFIG1 0x06
|
||||||
|
#define INIT_ERR_FUNC_SEND 0x09
|
||||||
|
#define INIT_ERR_CHECK_VALID 0xFF
|
||||||
|
|
||||||
|
/* Socket protocol type */
|
||||||
|
#define PROTO_TYPE_IP_RAW 0 //IP layer raw data
|
||||||
|
#define PROTO_TYPE_UDP 2 //UDP protocol
|
||||||
|
#define PROTO_TYPE_TCP 3 //TCP protocol
|
||||||
|
|
||||||
|
/* interrupt status */
|
||||||
|
/* The following are the states
|
||||||
|
* that GLOB_INT will generate */
|
||||||
|
#define GINT_STAT_UNREACH (1 << 0) //unreachable interrupt
|
||||||
|
#define GINT_STAT_IP_CONFLI (1 << 1) //IP conflict interrupt
|
||||||
|
#define GINT_STAT_PHY_CHANGE (1 << 2) //PHY state change interrupt
|
||||||
|
#define GINT_STAT_SOCKET (1 << 4) //socket related interrupt
|
||||||
|
|
||||||
|
/* The following are the states
|
||||||
|
* that Sn_INT will generate*/
|
||||||
|
#define SINT_STAT_RECV (1 << 2) //the socket receives data or the receive buffer is not empty
|
||||||
|
#define SINT_STAT_CONNECT (1 << 3) //connect successfully,generated in TCP mode
|
||||||
|
#define SINT_STAT_DISCONNECT (1 << 4) //disconnect,generated in TCP mode
|
||||||
|
#define SINT_STAT_TIM_OUT (1 << 6) //timeout disconnect,generated in TCP mode
|
||||||
|
|
||||||
|
|
||||||
|
/* Definitions for error constants. @ERR_T */
|
||||||
|
#define ERR_T
|
||||||
|
#define WCHNET_ERR_SUCCESS 0x00 //No error, everything OK
|
||||||
|
#define WCHNET_ERR_BUSY 0x10 //busy
|
||||||
|
#define WCHNET_ERR_MEM 0x11 //Out of memory error
|
||||||
|
#define WCHNET_ERR_BUF 0x12 //Buffer error
|
||||||
|
#define WCHNET_ERR_TIMEOUT 0x13 //Timeout
|
||||||
|
#define WCHNET_ERR_RTE 0x14 //Routing problem
|
||||||
|
#define WCHNET_ERR_ABRT 0x15 //Connection aborted
|
||||||
|
#define WCHNET_ERR_RST 0x16 //Connection reset
|
||||||
|
#define WCHNET_ERR_CLSD 0x17 //Connection closed
|
||||||
|
#define WCHNET_ERR_CONN 0x18 //Not connected
|
||||||
|
#define WCHNET_ERR_VAL 0x19 //Illegal value
|
||||||
|
#define WCHNET_ERR_ARG 0x1a //Illegal argument
|
||||||
|
#define WCHNET_ERR_USE 0x1b //Address in use
|
||||||
|
#define WCHNET_ERR_IF 0x1c //Low-level netif error
|
||||||
|
#define WCHNET_ERR_ISCONN 0x1d //Already connected
|
||||||
|
#define WCHNET_ERR_INPROGRESS 0x1e //Operation in progress
|
||||||
|
#define WCHNET_ERR_SOCKET_MEM 0X20 //Socket information error
|
||||||
|
#define WCHNET_ERR_UNSUPPORT_PROTO 0X21 //unsupported protocol type
|
||||||
|
#define WCHNET_RET_ABORT 0x5F //command process fail
|
||||||
|
#define WCHNET_ERR_UNKNOW 0xFA //unknow
|
||||||
|
|
||||||
|
/* unreachable condition related codes */
|
||||||
|
#define UNREACH_CODE_HOST 0 //host unreachable
|
||||||
|
#define UNREACH_CODE_NET 1 //network unreachable
|
||||||
|
#define UNREACH_CODE_PROTOCOL 2 //protocol unreachable
|
||||||
|
#define UNREACH_CODE_PROT 3 //port unreachable
|
||||||
|
/*For other values, please refer to the RFC792 document*/
|
||||||
|
|
||||||
|
/* TCP disconnect related codes */
|
||||||
|
#define TCP_CLOSE_NORMAL 0 //normal disconnect,a four-way handshake
|
||||||
|
#define TCP_CLOSE_RST 1 //reset the connection and close
|
||||||
|
#define TCP_CLOSE_ABANDON 2 //drop connection, and no termination message is sent
|
||||||
|
|
||||||
|
/* socket state code */
|
||||||
|
#define SOCK_STAT_CLOSED 0X00 //socket close
|
||||||
|
#define SOCK_STAT_OPEN 0X05 //socket open
|
||||||
|
|
||||||
|
/* TCP state code */
|
||||||
|
#define TCP_CLOSED 0 //TCP close
|
||||||
|
#define TCP_LISTEN 1 //TCP listening
|
||||||
|
#define TCP_SYN_SENT 2 //SYN send, connect request
|
||||||
|
#define TCP_SYN_RCVD 3 //SYN received, connection request received
|
||||||
|
#define TCP_ESTABLISHED 4 //TCP connection establishment
|
||||||
|
#define TCP_FIN_WAIT_1 5 //WAIT_1 state
|
||||||
|
#define TCP_FIN_WAIT_2 6 //WAIT_2 state
|
||||||
|
#define TCP_CLOSE_WAIT 7 //wait to close
|
||||||
|
#define TCP_CLOSING 8 //closing
|
||||||
|
#define TCP_LAST_ACK 9 //LAST_ACK
|
||||||
|
#define TCP_TIME_WAIT 10 //2MSL wait
|
||||||
|
|
||||||
|
/* The following values are fixed and cannot be changed */
|
||||||
|
#define WCHNET_MEM_ALIGN_SIZE(size) (((size) + WCHNET_MEM_ALIGNMENT - 1) & ~(WCHNET_MEM_ALIGNMENT - 1))
|
||||||
|
#define WCHNET_SIZE_IPRAW_PCB 0x1C //IPRAW PCB size
|
||||||
|
#define WCHNET_SIZE_UDP_PCB 0x20 //UDP PCB size
|
||||||
|
#define WCHNET_SIZE_TCP_PCB 0xB4 //TCP PCB size
|
||||||
|
#define WCHNET_SIZE_TCP_PCB_LISTEN 0x24 //TCP LISTEN PCB size
|
||||||
|
#define WCHNET_SIZE_IP_REASSDATA 0x20 //IP reassembled Management
|
||||||
|
#define WCHNET_SIZE_PBUF 0x10 //Packet Buf
|
||||||
|
#define WCHNET_SIZE_TCP_SEG 0x14 //TCP SEG structure
|
||||||
|
#define WCHNET_SIZE_MEM 0x08 //sizeof(struct mem)
|
||||||
|
#define WCHNET_SIZE_ARP_TABLE 0x18 //sizeof ARP table
|
||||||
|
|
||||||
|
#define WCHNET_MEMP_SIZE ((WCHNET_MEM_ALIGNMENT - 1) + \
|
||||||
|
(WCHNET_NUM_IPRAW * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IPRAW_PCB)) + \
|
||||||
|
(WCHNET_NUM_UDP * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_UDP_PCB)) + \
|
||||||
|
(WCHNET_NUM_TCP * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB)) + \
|
||||||
|
(WCHNET_NUM_TCP_LISTEN * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_PCB_LISTEN)) + \
|
||||||
|
(WCHNET_NUM_TCP_SEG * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_TCP_SEG)) + \
|
||||||
|
(WCHNET_NUM_IP_REASSDATA * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_IP_REASSDATA)) + \
|
||||||
|
(WCHNET_NUM_PBUF * WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF)) + \
|
||||||
|
(WCHNET_NUM_POOL_BUF * (WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_PBUF) + WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_POOL_BUF))))
|
||||||
|
|
||||||
|
#define HEAP_MEM_ALIGN_SIZE (WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_MEM))
|
||||||
|
#define WCHNET_RAM_HEAP_SIZE (WCHNET_MEM_ALIGN_SIZE(WCHNET_MEM_HEAP_SIZE) + HEAP_MEM_ALIGN_SIZE )
|
||||||
|
#define WCHNET_RAM_ARP_TABLE_SIZE (WCHNET_MEM_ALIGN_SIZE(WCHNET_SIZE_ARP_TABLE) * WCHNET_NUM_ARP_TABLE)
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t length;
|
||||||
|
uint32_t buffer;
|
||||||
|
}ETHFrameType;
|
||||||
|
|
||||||
|
/* LED callback type */
|
||||||
|
typedef void (*led_callback)( uint8_t setbit );
|
||||||
|
|
||||||
|
/* net send callback type */
|
||||||
|
typedef uint32_t (*eth_tx_set )( uint16_t len, uint32_t *pBuff );
|
||||||
|
|
||||||
|
/* net receive callback type */
|
||||||
|
typedef uint32_t (*eth_rx_set )( ETHFrameType *pkt );
|
||||||
|
|
||||||
|
/* DNS callback type */
|
||||||
|
typedef void (*dns_callback)( const char *name, uint8_t *ipaddr, void *callback_arg );
|
||||||
|
|
||||||
|
/* DHCP callback type */
|
||||||
|
typedef uint8_t (*dhcp_callback)( uint8_t status, void * );
|
||||||
|
|
||||||
|
/* socket receive callback type */
|
||||||
|
struct _SOCK_INF;
|
||||||
|
typedef void (*pSockRecv)( struct _SOCK_INF *, uint32_t, uint16_t, uint8_t *, uint32_t);
|
||||||
|
|
||||||
|
typedef uint8_t (*pTcpVerifyConnection)(uint32_t src_ip, uint16_t src_port, uint16_t dest_port);
|
||||||
|
|
||||||
|
/* Socket information struct */
|
||||||
|
typedef struct _SOCK_INF
|
||||||
|
{
|
||||||
|
uint32_t IntStatus; //interrupt state
|
||||||
|
uint32_t SockIndex; //Socket index value
|
||||||
|
uint32_t RecvStartPoint; //Start pointer of the receive buffer
|
||||||
|
uint32_t RecvBufLen; //Receive buffer length
|
||||||
|
uint32_t RecvCurPoint; //current pointer to receive buffer
|
||||||
|
uint32_t RecvReadPoint; //The read pointer of the receive buffer
|
||||||
|
uint32_t RecvRemLen; //The length of the remaining data in the receive buffer
|
||||||
|
uint32_t ProtoType; //protocol type
|
||||||
|
uint32_t SockStatus; //Low byte Socket state, the next low byte is TCP state, only meaningful in TCP mode
|
||||||
|
uint32_t DesPort; //destination port
|
||||||
|
uint32_t SourPort; //Source port, protocol type in IPRAW mode
|
||||||
|
uint8_t IPAddr[4]; //Socket destination IP address
|
||||||
|
void *Resv1; //Reserved, for internal use, for saving individual PCBs
|
||||||
|
void *Resv2; //Reserved, used internally, used by TCP Server
|
||||||
|
pSockRecv AppCallBack; //receive callback function
|
||||||
|
} SOCK_INF;
|
||||||
|
|
||||||
|
struct _WCH_CFG
|
||||||
|
{
|
||||||
|
uint32_t TxBufSize; //MAC send buffer size, reserved for use
|
||||||
|
uint32_t TCPMss; //TCP MSS size
|
||||||
|
uint32_t HeapSize; //heap memory size
|
||||||
|
uint32_t ARPTableNum; //Number of ARP lists
|
||||||
|
uint32_t MiscConfig0; //Miscellaneous Configuration 0
|
||||||
|
/* Bit 0 TCP send buffer copy 1: copy, 0: not copy */
|
||||||
|
/* Bit 1 TCP receive replication optimization, used for internal debugging */
|
||||||
|
/* bit 2 delete oldest TCP connection 1: enable, 0: disable */
|
||||||
|
/* Bits 3-7 Number of PBUFs of IP segments */
|
||||||
|
/* Bit 8 TCP Delay ACK disable */
|
||||||
|
uint32_t MiscConfig1; //Miscellaneous Configuration 1
|
||||||
|
/* Bits 0-7 Number of Sockets*/
|
||||||
|
/* Bits 8-12 Reserved */
|
||||||
|
/* Bit 13 PING enable, 1: On 0: Off */
|
||||||
|
/* Bits 14-18 TCP retransmission times */
|
||||||
|
/* Bits 19-23 TCP retransmission period, in 50 milliseconds */
|
||||||
|
/* bit 25 send failed retry, 1: enable, 0: disable */
|
||||||
|
/* bit 26 Select whether to perform IPv4 checksum check on
|
||||||
|
* the TCP/UDP/ICMP header of the received frame payload by hardware,
|
||||||
|
* and calculate and insert the checksum of the IP header and payload of the sent frame by hardware.*/
|
||||||
|
/* Bits 27-31 period (in 250 milliseconds) of Fine DHCP periodic process */
|
||||||
|
led_callback led_link; //PHY Link Status Indicator
|
||||||
|
led_callback led_data; //Ethernet communication indicator
|
||||||
|
eth_tx_set net_send; //Ethernet send
|
||||||
|
eth_rx_set net_recv; //Ethernet receive
|
||||||
|
uint32_t CheckValid; //Configuration value valid flag, fixed value @WCHNET_CFG_VALID
|
||||||
|
};
|
||||||
|
|
||||||
|
struct _NET_SYS
|
||||||
|
{
|
||||||
|
uint8_t IPAddr[4]; //IP address
|
||||||
|
uint8_t GWIPAddr[4]; //Gateway IP address
|
||||||
|
uint8_t MASKAddr[4]; //subnet mask
|
||||||
|
uint8_t MacAddr[8]; //MAC address
|
||||||
|
uint8_t UnreachIPAddr[4]; //Unreachable IP address
|
||||||
|
uint32_t RetranCount; //number of retries,default is 10 times
|
||||||
|
uint32_t RetranPeriod; //Retry period, unit MS, default 500MS
|
||||||
|
uint32_t PHYStat; //PHY state code
|
||||||
|
uint32_t NetStat; //The status of the Ethernet, including whether it is open, etc.
|
||||||
|
uint32_t MackFilt; //MAC filtering, the default is to receive broadcasts, receive local MAC
|
||||||
|
uint32_t GlobIntStatus; //global interrupt
|
||||||
|
uint32_t UnreachCode; //unreachable code
|
||||||
|
uint32_t UnreachProto; //unreachable protocol
|
||||||
|
uint32_t UnreachPort; //unreachable port
|
||||||
|
uint32_t SendFlag;
|
||||||
|
uint32_t Flags;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* KEEP LIVE configuration structure */
|
||||||
|
struct _KEEP_CFG
|
||||||
|
{
|
||||||
|
uint32_t KLIdle; //KEEPLIVE idle time, in ms
|
||||||
|
uint32_t KLIntvl; //KEEPLIVE period, in ms
|
||||||
|
uint32_t KLCount; //KEEPLIVE times
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Library initialization .
|
||||||
|
*
|
||||||
|
* @param ip - IP address pointer
|
||||||
|
* @param gwip - Gateway address pointer
|
||||||
|
* @param mask - Subnet mask pointer
|
||||||
|
* @param macaddr - MAC address pointer
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_Init(const uint8_t *ip, const uint8_t *gwip, const uint8_t *mask, const uint8_t *macaddr);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief get library version
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return library version
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_GetVer(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get MAC address.
|
||||||
|
*
|
||||||
|
* @param(in) macaddr - MAC address
|
||||||
|
*
|
||||||
|
* @param(out) MAC address
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_GetMacAddr(uint8_t *macaddr);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Library parameter configuration.
|
||||||
|
*
|
||||||
|
* @param cfg - Configuration parameter @_WCH_CFG
|
||||||
|
*
|
||||||
|
* @return Library configuration initialization state @CFG_INIT_STAT
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_ConfigLIB(struct _WCH_CFG *cfg);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Handle periodic tasks in the protocol stack
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_PeriodicHandle(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Ethernet data input. Always called in the main program,
|
||||||
|
* or called after the reception interrupt is detected.
|
||||||
|
*
|
||||||
|
* @param
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_NetInput( void );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Ethernet interrupt service function. Called after
|
||||||
|
* Ethernet interrupt is generated.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_ETHIsr(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get PHY status
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return PHY status @PHY_STAT
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_GetPHYStatus(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Query global interrupt status.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return GLOB_INT
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_QueryGlobalInt(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read global interrupt and clear it.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return GLOB_INT
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_GetGlobalInt(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief create socket
|
||||||
|
*
|
||||||
|
* @param(in) *socketid - socket variable pointer
|
||||||
|
* @param socinf - Configuration parameters for creating sockets @SOCK_INF
|
||||||
|
*
|
||||||
|
* @param(out) *socketid - socket value
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_SocketCreat( uint8_t *socketid, SOCK_INF *socinf);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Socket sends data.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
* @param *buf - the first address of send buffer
|
||||||
|
* @param(in) *len - pointer to the length of the data expected to be sent
|
||||||
|
*
|
||||||
|
* @param(out) *len - pointer to the length of the data sent actually
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_SocketSend( uint8_t socketid, uint8_t *buf, uint32_t *len);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Socket receives data.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
* @param *buf - the first address of receive buffer
|
||||||
|
* @param(in) *len - pointer to the length of the data expected to be read
|
||||||
|
*
|
||||||
|
* @param(out) *buf - the first address of data buffer
|
||||||
|
* @param(out) *len - pointer to the length of the data read actually
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_SocketRecv( uint8_t socketid, uint8_t *buf, uint32_t *len);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get socket interrupt, and clear socket interrupt.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
*
|
||||||
|
* @return Sn_INT
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_GetSocketInt( uint8_t socketid );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the length of the data received by socket.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
* @param(in) *bufaddr - the first address of receive buffer
|
||||||
|
*
|
||||||
|
* @param(out) *bufaddr - the first address of data buffer
|
||||||
|
*
|
||||||
|
* @return the length of the data
|
||||||
|
*/
|
||||||
|
uint32_t WCHNET_SocketRecvLen( uint8_t socketid, uint32_t *bufaddr);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief TCP connect. Used in TCP Client mode.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_SocketConnect( uint8_t socketid);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief TCP listen. Used in TCP SERVER mode.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_SocketListen( uint8_t socketid);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Close socket.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
* @param mode - the way of disconnection.Used in TCP connection.
|
||||||
|
* @TCP disconnect related codes
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_SocketClose( uint8_t socketid, uint8_t mode );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Modify socket receive buffer.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
* @param bufaddr - Address of the receive buffer
|
||||||
|
* @param bufsize - Size of the receive buffer
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_ModifyRecvBuf( uint8_t socketid, uint32_t bufaddr, uint32_t bufsize);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief UDP send, specify the target IP and target port
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
* @param *buf - Address of the sent data
|
||||||
|
* @param(in) *slen - Address of the sent length
|
||||||
|
* @param *sip - destination IP address
|
||||||
|
* @param port - destination port
|
||||||
|
*
|
||||||
|
* @param(out) *slen - actual length sent
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_SocketUdpSendTo( uint8_t socketid, uint8_t *buf, uint32_t *slen, uint8_t *sip, uint16_t port);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Convert ASCII address to network address.
|
||||||
|
*
|
||||||
|
* @param *cp - ASCII address to be converted, such as "192.168.1.2"
|
||||||
|
* @param(in) *addr - First address of the memory stored in the converted network address
|
||||||
|
* @param(out) *addr - Converted network address, such as 0xC0A80102
|
||||||
|
* @return 0 - Success. Others - Failure.
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_Aton(const char *cp, uint8_t *addr);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Convert network address to ASCII address.
|
||||||
|
*
|
||||||
|
* @param *ipaddr - socket id value
|
||||||
|
*
|
||||||
|
* @return Converted ASCII address
|
||||||
|
*/
|
||||||
|
uint8_t *WCHNET_Ntoa( uint8_t *ipaddr);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set socket TTL.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
* @param ttl - TTL value
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_SetSocketTTL( uint8_t socketid, uint8_t ttl);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Start TCP retry sending immediately.
|
||||||
|
*
|
||||||
|
* @param socketid - TTL value
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_RetrySendUnack( uint8_t socketid);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Query the packets that are not sent successfully.
|
||||||
|
*
|
||||||
|
* @param socketid - TTL value
|
||||||
|
* @param(in) *addrlist - pointer to the address of the address list
|
||||||
|
* @param lislen - Length of the list
|
||||||
|
*
|
||||||
|
* @param(out) *addrlist - Address list of the data packets that are not sent successfully
|
||||||
|
*
|
||||||
|
* @return Number of unsent and unacknowledged segments
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_QueryUnack( uint8_t socketid, uint32_t *addrlist, uint16_t lislen );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Start DHCP.
|
||||||
|
*
|
||||||
|
* @param dhcp - Application layer callback function
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_DHCPStart( dhcp_callback dhcp );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop DHCP.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_DHCPStop( void );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure DHCP host name.
|
||||||
|
*
|
||||||
|
* @param *name - First address of DHCP host name
|
||||||
|
*
|
||||||
|
* @return 0 - Success. Others - Failure.
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_DHCPSetHostname(char *name);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize the resolver: set up the UDP pcb and configure the default server
|
||||||
|
*
|
||||||
|
* @param *dnsip - the IP address of dns server
|
||||||
|
* @param port - the port number of dns server
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_InitDNS( uint8_t *dnsip, uint16_t port);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop DNS.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_DNSStop(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Resolve a hostname (string) into an IP address.
|
||||||
|
*
|
||||||
|
* @param hostname - the hostname that is to be queried
|
||||||
|
* @param addr - pointer to a struct ip_addr where to store the address if it is already
|
||||||
|
* cached in the dns_table (only valid if ERR_OK is returned!)
|
||||||
|
* @param found - a callback function to be called on success, failure or timeout (only if
|
||||||
|
* ERR_INPROGRESS is returned!)
|
||||||
|
* @param arg - argument to pass to the callback function
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
* WCHNET_ERR_SUCCESS if hostname is a valid IP address string or the host name is already in the local names table.
|
||||||
|
* ERR_INPROGRESS enqueue a request to be sent to the DNS server for resolution if no errors are present.
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_HostNameGetIp( const char *hostname, uint8_t *addr, dns_callback found, void *arg );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure KEEP LIVE parameter.
|
||||||
|
*
|
||||||
|
* @param *cfg - KEEPLIVE configuration parameter
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_ConfigKeepLive( struct _KEEP_CFG *cfg );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure ARP retransmission parameters.
|
||||||
|
*
|
||||||
|
* @param retry_period - ARP retransmission period, the default value is 10, the unit is 100ms
|
||||||
|
* retry_cnt - The number of ARP retransmissions, the default value is 3.
|
||||||
|
* When the value of the retry_cnt is 0xff, it will be retried
|
||||||
|
* until the MAC address of the device is obtained.
|
||||||
|
* Arp_Entry_timeout_s - the time an ARP entry stays valid after its last update.
|
||||||
|
* the default value is 300, the unit is 1s
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_ARPRetryCfg(uint8_t retry_period, uint8_t retry_cnt, uint16_t Arp_Entry_timeout_s);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure socket KEEP LIVE enable.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
* @param enable - 1: Enabled. 0: Disabled.
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_SocketSetKeepLive( uint8_t socketid, uint8_t enable );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure PHY state
|
||||||
|
*
|
||||||
|
* @param phy_stat - PHY state
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void WCHNET_PhyStatus( uint32_t phy_stat );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure socket Nagle Func.
|
||||||
|
*
|
||||||
|
* @param socketid - socket id value
|
||||||
|
* @param enable - 1: Enabled. 0: Disabled.
|
||||||
|
*
|
||||||
|
* @return @ERR_T
|
||||||
|
*/
|
||||||
|
uint8_t WCHNET_SocketSetNagle( uint8_t socketid, uint8_t enable );
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,230 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_adc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* ADC firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_ADC_H
|
||||||
|
#define __CH32V30x_ADC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* ADC Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
|
||||||
|
dual mode.
|
||||||
|
This parameter can be a value of @ref ADC_mode */
|
||||||
|
|
||||||
|
FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
|
||||||
|
Scan (multichannels) or Single (one channel) mode.
|
||||||
|
This parameter can be set to ENABLE or DISABLE */
|
||||||
|
|
||||||
|
FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
|
||||||
|
Continuous or Single mode.
|
||||||
|
This parameter can be set to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
|
||||||
|
to digital conversion of regular channels. This parameter
|
||||||
|
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||||
|
|
||||||
|
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
|
||||||
|
This parameter can be a value of @ref ADC_data_align */
|
||||||
|
|
||||||
|
uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
|
||||||
|
using the sequencer for regular channel group.
|
||||||
|
This parameter must range from 1 to 16. */
|
||||||
|
|
||||||
|
uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref ADC_OutputBuffer */
|
||||||
|
|
||||||
|
uint32_t ADC_Pga; /* Specifies the PGA gain multiple.
|
||||||
|
This parameter can be a value of @ref ADC_Pga */
|
||||||
|
}ADC_InitTypeDef;
|
||||||
|
|
||||||
|
/* ADC_mode */
|
||||||
|
#define ADC_Mode_Independent ((uint32_t)0x00000000)
|
||||||
|
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
|
||||||
|
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
|
||||||
|
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
|
||||||
|
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
|
||||||
|
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
|
||||||
|
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
|
||||||
|
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
|
||||||
|
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
|
||||||
|
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
|
||||||
|
|
||||||
|
/* ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||||
|
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
|
||||||
|
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
|
||||||
|
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
|
||||||
|
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
|
||||||
|
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
|
||||||
|
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
|
||||||
|
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)
|
||||||
|
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)
|
||||||
|
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)
|
||||||
|
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000)
|
||||||
|
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000)
|
||||||
|
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000)
|
||||||
|
|
||||||
|
|
||||||
|
/* ADC_data_align */
|
||||||
|
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||||
|
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||||
|
|
||||||
|
/* ADC_channels */
|
||||||
|
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||||
|
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||||
|
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||||
|
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||||
|
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||||
|
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||||
|
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||||
|
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||||
|
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||||
|
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||||
|
#define ADC_Channel_10 ((uint8_t)0x0A)
|
||||||
|
#define ADC_Channel_11 ((uint8_t)0x0B)
|
||||||
|
#define ADC_Channel_12 ((uint8_t)0x0C)
|
||||||
|
#define ADC_Channel_13 ((uint8_t)0x0D)
|
||||||
|
#define ADC_Channel_14 ((uint8_t)0x0E)
|
||||||
|
#define ADC_Channel_15 ((uint8_t)0x0F)
|
||||||
|
#define ADC_Channel_16 ((uint8_t)0x10)
|
||||||
|
#define ADC_Channel_17 ((uint8_t)0x11)
|
||||||
|
|
||||||
|
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||||
|
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
|
||||||
|
|
||||||
|
/*ADC_output_buffer*/
|
||||||
|
#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000)
|
||||||
|
#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/*ADC_pga*/
|
||||||
|
#define ADC_Pga_1 ((uint32_t)0x00000000)
|
||||||
|
#define ADC_Pga_4 ((uint32_t)0x08000000)
|
||||||
|
#define ADC_Pga_16 ((uint32_t)0x10000000)
|
||||||
|
#define ADC_Pga_64 ((uint32_t)0x18000000)
|
||||||
|
|
||||||
|
/* ADC_sampling_time */
|
||||||
|
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
|
||||||
|
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
|
||||||
|
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
|
||||||
|
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
|
||||||
|
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
|
||||||
|
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
|
||||||
|
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
|
||||||
|
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
|
||||||
|
|
||||||
|
/* ADC_external_trigger_sources_for_injected_channels_conversion */
|
||||||
|
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000)
|
||||||
|
|
||||||
|
|
||||||
|
/* ADC_injected_channel_selection */
|
||||||
|
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||||
|
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||||
|
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
|
||||||
|
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
|
||||||
|
|
||||||
|
/* ADC_analog_watchdog_selection */
|
||||||
|
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||||
|
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||||
|
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||||
|
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||||
|
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||||
|
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||||
|
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* ADC_interrupts_definition */
|
||||||
|
#define ADC_IT_EOC ((uint16_t)0x0220)
|
||||||
|
#define ADC_IT_AWD ((uint16_t)0x0140)
|
||||||
|
#define ADC_IT_JEOC ((uint16_t)0x0480)
|
||||||
|
|
||||||
|
/* ADC_flags_definition */
|
||||||
|
#define ADC_FLAG_AWD ((uint8_t)0x01)
|
||||||
|
#define ADC_FLAG_EOC ((uint8_t)0x02)
|
||||||
|
#define ADC_FLAG_JEOC ((uint8_t)0x04)
|
||||||
|
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
|
||||||
|
#define ADC_FLAG_STRT ((uint8_t)0x10)
|
||||||
|
|
||||||
|
|
||||||
|
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||||
|
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||||
|
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||||
|
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
|
||||||
|
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_StartCalibration(ADC_TypeDef* ADCx);
|
||||||
|
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||||
|
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||||
|
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||||
|
uint32_t ADC_GetDualModeConversionValue(void);
|
||||||
|
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||||
|
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||||
|
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
||||||
|
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||||
|
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||||
|
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||||
|
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||||
|
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||||
|
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
||||||
|
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||||
|
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||||
|
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||||
|
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||||
|
s32 TempSensor_Volt_To_Temper(s32 Value);
|
||||||
|
void ADC_BufferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
int16_t Get_CalibrationValue(ADC_TypeDef* ADCx);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,99 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_bkp.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* BKP firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_BKP_H
|
||||||
|
#define __CH32V30x_BKP_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* Tamper_Pin_active_level */
|
||||||
|
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
|
||||||
|
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
/* RTC_output_source_to_output_on_the_Tamper_pin */
|
||||||
|
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
|
||||||
|
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
|
||||||
|
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
|
||||||
|
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
|
||||||
|
|
||||||
|
/* Data_Backup_Register */
|
||||||
|
#define BKP_DR1 ((uint16_t)0x0004)
|
||||||
|
#define BKP_DR2 ((uint16_t)0x0008)
|
||||||
|
#define BKP_DR3 ((uint16_t)0x000C)
|
||||||
|
#define BKP_DR4 ((uint16_t)0x0010)
|
||||||
|
#define BKP_DR5 ((uint16_t)0x0014)
|
||||||
|
#define BKP_DR6 ((uint16_t)0x0018)
|
||||||
|
#define BKP_DR7 ((uint16_t)0x001C)
|
||||||
|
#define BKP_DR8 ((uint16_t)0x0020)
|
||||||
|
#define BKP_DR9 ((uint16_t)0x0024)
|
||||||
|
#define BKP_DR10 ((uint16_t)0x0028)
|
||||||
|
#define BKP_DR11 ((uint16_t)0x0040)
|
||||||
|
#define BKP_DR12 ((uint16_t)0x0044)
|
||||||
|
#define BKP_DR13 ((uint16_t)0x0048)
|
||||||
|
#define BKP_DR14 ((uint16_t)0x004C)
|
||||||
|
#define BKP_DR15 ((uint16_t)0x0050)
|
||||||
|
#define BKP_DR16 ((uint16_t)0x0054)
|
||||||
|
#define BKP_DR17 ((uint16_t)0x0058)
|
||||||
|
#define BKP_DR18 ((uint16_t)0x005C)
|
||||||
|
#define BKP_DR19 ((uint16_t)0x0060)
|
||||||
|
#define BKP_DR20 ((uint16_t)0x0064)
|
||||||
|
#define BKP_DR21 ((uint16_t)0x0068)
|
||||||
|
#define BKP_DR22 ((uint16_t)0x006C)
|
||||||
|
#define BKP_DR23 ((uint16_t)0x0070)
|
||||||
|
#define BKP_DR24 ((uint16_t)0x0074)
|
||||||
|
#define BKP_DR25 ((uint16_t)0x0078)
|
||||||
|
#define BKP_DR26 ((uint16_t)0x007C)
|
||||||
|
#define BKP_DR27 ((uint16_t)0x0080)
|
||||||
|
#define BKP_DR28 ((uint16_t)0x0084)
|
||||||
|
#define BKP_DR29 ((uint16_t)0x0088)
|
||||||
|
#define BKP_DR30 ((uint16_t)0x008C)
|
||||||
|
#define BKP_DR31 ((uint16_t)0x0090)
|
||||||
|
#define BKP_DR32 ((uint16_t)0x0094)
|
||||||
|
#define BKP_DR33 ((uint16_t)0x0098)
|
||||||
|
#define BKP_DR34 ((uint16_t)0x009C)
|
||||||
|
#define BKP_DR35 ((uint16_t)0x00A0)
|
||||||
|
#define BKP_DR36 ((uint16_t)0x00A4)
|
||||||
|
#define BKP_DR37 ((uint16_t)0x00A8)
|
||||||
|
#define BKP_DR38 ((uint16_t)0x00AC)
|
||||||
|
#define BKP_DR39 ((uint16_t)0x00B0)
|
||||||
|
#define BKP_DR40 ((uint16_t)0x00B4)
|
||||||
|
#define BKP_DR41 ((uint16_t)0x00B8)
|
||||||
|
#define BKP_DR42 ((uint16_t)0x00BC)
|
||||||
|
|
||||||
|
|
||||||
|
void BKP_DeInit(void);
|
||||||
|
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
|
||||||
|
void BKP_TamperPinCmd(FunctionalState NewState);
|
||||||
|
void BKP_ITConfig(FunctionalState NewState);
|
||||||
|
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
|
||||||
|
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
|
||||||
|
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
|
||||||
|
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
|
||||||
|
FlagStatus BKP_GetFlagStatus(void);
|
||||||
|
void BKP_ClearFlag(void);
|
||||||
|
ITStatus BKP_GetITStatus(void);
|
||||||
|
void BKP_ClearITPendingBit(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,376 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_can.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* CAN firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_CAN_H
|
||||||
|
#define __CH32V30x_CAN_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* CAN init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t CAN_Prescaler; /* Specifies the length of a time quantum.
|
||||||
|
It ranges from 1 to 1024. */
|
||||||
|
|
||||||
|
uint8_t CAN_Mode; /* Specifies the CAN operating mode.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_operating_mode */
|
||||||
|
|
||||||
|
uint8_t CAN_SJW; /* Specifies the maximum number of time quanta
|
||||||
|
the CAN hardware is allowed to lengthen or
|
||||||
|
shorten a bit to perform resynchronization.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_synchronisation_jump_width */
|
||||||
|
|
||||||
|
uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit
|
||||||
|
Segment 1. This parameter can be a value of
|
||||||
|
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||||
|
|
||||||
|
uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit
|
||||||
|
Segment 2.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_time_quantum_in_bit_segment_2 */
|
||||||
|
|
||||||
|
FunctionalState CAN_TTCM; /* Enable or disable the time triggered
|
||||||
|
communication mode. This parameter can be set
|
||||||
|
either to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off
|
||||||
|
management. This parameter can be set either
|
||||||
|
to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode.
|
||||||
|
This parameter can be set either to ENABLE or
|
||||||
|
DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_NART; /* Enable or disable the no-automatic
|
||||||
|
retransmission mode. This parameter can be
|
||||||
|
set either to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode.
|
||||||
|
This parameter can be set either to ENABLE
|
||||||
|
or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority.
|
||||||
|
This parameter can be set either to ENABLE
|
||||||
|
or DISABLE. */
|
||||||
|
} CAN_InitTypeDef;
|
||||||
|
|
||||||
|
/* CAN filter init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit
|
||||||
|
configuration, first one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit
|
||||||
|
configuration, second one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number,
|
||||||
|
according to the mode (MSBs for a 32-bit configuration,
|
||||||
|
first one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number,
|
||||||
|
according to the mode (LSBs for a 32-bit configuration,
|
||||||
|
second one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||||
|
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||||
|
|
||||||
|
uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||||
|
|
||||||
|
uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized.
|
||||||
|
This parameter can be a value of @ref CAN_filter_mode */
|
||||||
|
|
||||||
|
uint8_t CAN_FilterScale; /* Specifies the filter scale.
|
||||||
|
This parameter can be a value of @ref CAN_filter_scale */
|
||||||
|
|
||||||
|
FunctionalState CAN_FilterActivation; /* Enable or disable the filter.
|
||||||
|
This parameter can be set either to ENABLE or DISABLE. */
|
||||||
|
} CAN_FilterInitTypeDef;
|
||||||
|
|
||||||
|
/* CAN Tx message structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t StdId; /* Specifies the standard identifier.
|
||||||
|
This parameter can be a value between 0 to 0x7FF. */
|
||||||
|
|
||||||
|
uint32_t ExtId; /* Specifies the extended identifier.
|
||||||
|
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||||
|
|
||||||
|
uint8_t IDE; /* Specifies the type of identifier for the message that
|
||||||
|
will be transmitted. This parameter can be a value
|
||||||
|
of @ref CAN_identifier_type */
|
||||||
|
|
||||||
|
uint8_t RTR; /* Specifies the type of frame for the message that will
|
||||||
|
be transmitted. This parameter can be a value of
|
||||||
|
@ref CAN_remote_transmission_request */
|
||||||
|
|
||||||
|
uint8_t DLC; /* Specifies the length of the frame that will be
|
||||||
|
transmitted. This parameter can be a value between
|
||||||
|
0 to 8 */
|
||||||
|
|
||||||
|
uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0
|
||||||
|
to 0xFF. */
|
||||||
|
} CanTxMsg;
|
||||||
|
|
||||||
|
/* CAN Rx message structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t StdId; /* Specifies the standard identifier.
|
||||||
|
This parameter can be a value between 0 to 0x7FF. */
|
||||||
|
|
||||||
|
uint32_t ExtId; /* Specifies the extended identifier.
|
||||||
|
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||||
|
|
||||||
|
uint8_t IDE; /* Specifies the type of identifier for the message that
|
||||||
|
will be received. This parameter can be a value of
|
||||||
|
@ref CAN_identifier_type */
|
||||||
|
|
||||||
|
uint8_t RTR; /* Specifies the type of frame for the received message.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_remote_transmission_request */
|
||||||
|
|
||||||
|
uint8_t DLC; /* Specifies the length of the frame that will be received.
|
||||||
|
This parameter can be a value between 0 to 8 */
|
||||||
|
|
||||||
|
uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to
|
||||||
|
0xFF. */
|
||||||
|
|
||||||
|
uint8_t FMI; /* Specifies the index of the filter the message stored in
|
||||||
|
the mailbox passes through. This parameter can be a
|
||||||
|
value between 0 to 0xFF */
|
||||||
|
} CanRxMsg;
|
||||||
|
|
||||||
|
/* CAN_sleep_constants */
|
||||||
|
#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */
|
||||||
|
#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */
|
||||||
|
|
||||||
|
/* CAN_Mode */
|
||||||
|
#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */
|
||||||
|
#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */
|
||||||
|
#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */
|
||||||
|
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */
|
||||||
|
|
||||||
|
/* CAN_Operating_Mode */
|
||||||
|
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */
|
||||||
|
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */
|
||||||
|
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */
|
||||||
|
|
||||||
|
/* CAN_Mode_Status */
|
||||||
|
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */
|
||||||
|
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */
|
||||||
|
|
||||||
|
/* CAN_synchronisation_jump_width */
|
||||||
|
#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */
|
||||||
|
#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */
|
||||||
|
#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */
|
||||||
|
#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */
|
||||||
|
|
||||||
|
/* CAN_time_quantum_in_bit_segment_1 */
|
||||||
|
#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */
|
||||||
|
#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */
|
||||||
|
#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */
|
||||||
|
#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */
|
||||||
|
#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */
|
||||||
|
#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */
|
||||||
|
#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */
|
||||||
|
#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */
|
||||||
|
#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */
|
||||||
|
#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */
|
||||||
|
#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */
|
||||||
|
#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */
|
||||||
|
#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */
|
||||||
|
#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */
|
||||||
|
#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */
|
||||||
|
#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */
|
||||||
|
|
||||||
|
/* CAN_time_quantum_in_bit_segment_2 */
|
||||||
|
#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */
|
||||||
|
#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */
|
||||||
|
#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */
|
||||||
|
#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */
|
||||||
|
#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */
|
||||||
|
#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */
|
||||||
|
#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */
|
||||||
|
#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */
|
||||||
|
|
||||||
|
/* CAN_filter_mode */
|
||||||
|
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */
|
||||||
|
#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */
|
||||||
|
|
||||||
|
/* CAN_filter_scale */
|
||||||
|
#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */
|
||||||
|
#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */
|
||||||
|
|
||||||
|
/* CAN_filter_FIFO */
|
||||||
|
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */
|
||||||
|
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */
|
||||||
|
|
||||||
|
/* CAN_identifier_type */
|
||||||
|
#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */
|
||||||
|
#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */
|
||||||
|
|
||||||
|
/* CAN_remote_transmission_request */
|
||||||
|
#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */
|
||||||
|
#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */
|
||||||
|
|
||||||
|
/* CAN_transmit_constants */
|
||||||
|
#define CAN_TxStatus_Failed ((uint8_t)0x00)/* CAN transmission failed */
|
||||||
|
#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */
|
||||||
|
#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */
|
||||||
|
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */
|
||||||
|
|
||||||
|
/* CAN_receive_FIFO_number_constants */
|
||||||
|
#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */
|
||||||
|
#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */
|
||||||
|
|
||||||
|
/* CAN_sleep_constants */
|
||||||
|
#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */
|
||||||
|
#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */
|
||||||
|
|
||||||
|
/* CAN_wake_up_constants */
|
||||||
|
#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */
|
||||||
|
#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */
|
||||||
|
|
||||||
|
/* CAN_Error_Code_constants */
|
||||||
|
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */
|
||||||
|
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */
|
||||||
|
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */
|
||||||
|
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */
|
||||||
|
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */
|
||||||
|
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */
|
||||||
|
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */
|
||||||
|
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */
|
||||||
|
|
||||||
|
|
||||||
|
/* CAN_flags */
|
||||||
|
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||||
|
* and CAN_ClearFlag() functions.
|
||||||
|
* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function.
|
||||||
|
*/
|
||||||
|
/* Transmit Flags */
|
||||||
|
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */
|
||||||
|
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */
|
||||||
|
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */
|
||||||
|
|
||||||
|
/* Receive Flags */
|
||||||
|
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */
|
||||||
|
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */
|
||||||
|
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */
|
||||||
|
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */
|
||||||
|
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */
|
||||||
|
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */
|
||||||
|
|
||||||
|
/* Operating Mode Flags */
|
||||||
|
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */
|
||||||
|
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */
|
||||||
|
/* Note:
|
||||||
|
*When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||||
|
*In this case the SLAK bit can be polled.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Error Flags */
|
||||||
|
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */
|
||||||
|
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */
|
||||||
|
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */
|
||||||
|
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */
|
||||||
|
|
||||||
|
|
||||||
|
/* CAN_interrupts */
|
||||||
|
#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/
|
||||||
|
|
||||||
|
/* Receive Interrupts */
|
||||||
|
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/
|
||||||
|
#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/
|
||||||
|
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/
|
||||||
|
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/
|
||||||
|
#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/
|
||||||
|
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/
|
||||||
|
|
||||||
|
/* Operating Mode Interrupts */
|
||||||
|
#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/
|
||||||
|
#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/
|
||||||
|
|
||||||
|
/* Error Interrupts */
|
||||||
|
#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/
|
||||||
|
#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/
|
||||||
|
#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/
|
||||||
|
#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/
|
||||||
|
#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/
|
||||||
|
|
||||||
|
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||||
|
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||||
|
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||||
|
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||||
|
|
||||||
|
/* CAN_Legacy */
|
||||||
|
#define CANINITFAILED CAN_InitStatus_Failed
|
||||||
|
#define CANINITOK CAN_InitStatus_Success
|
||||||
|
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||||
|
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||||
|
#define CAN_ID_STD CAN_Id_Standard
|
||||||
|
#define CAN_ID_EXT CAN_Id_Extended
|
||||||
|
#define CAN_RTR_DATA CAN_RTR_Data
|
||||||
|
#define CAN_RTR_REMOTE CAN_RTR_Remote
|
||||||
|
#define CANTXFAILE CAN_TxStatus_Failed
|
||||||
|
#define CANTXOK CAN_TxStatus_Ok
|
||||||
|
#define CANTXPENDING CAN_TxStatus_Pending
|
||||||
|
#define CAN_NO_MB CAN_TxStatus_NoMailBox
|
||||||
|
#define CANSLEEPFAILED CAN_Sleep_Failed
|
||||||
|
#define CANSLEEPOK CAN_Sleep_Ok
|
||||||
|
#define CANWAKEUPFAILED CAN_WakeUp_Failed
|
||||||
|
#define CANWAKEUPOK CAN_WakeUp_Ok
|
||||||
|
|
||||||
|
|
||||||
|
void CAN_DeInit(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
|
||||||
|
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
|
||||||
|
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
|
||||||
|
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||||
|
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||||
|
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||||
|
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
|
||||||
|
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
|
||||||
|
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
|
||||||
|
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
|
||||||
|
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||||
|
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||||
|
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
|
||||||
|
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
|
||||||
|
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
|
||||||
|
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||||
|
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||||
|
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||||
|
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,39 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_crc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* CRC firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_CRC_H
|
||||||
|
#define __CH32V30x_CRC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
void CRC_ResetDR(void);
|
||||||
|
uint32_t CRC_CalcCRC(uint32_t Data);
|
||||||
|
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||||
|
uint32_t CRC_GetCRC(void);
|
||||||
|
void CRC_SetIDRegister(uint8_t IDValue);
|
||||||
|
uint8_t CRC_GetIDRegister(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,122 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dac.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* DAC firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_DAC_H
|
||||||
|
#define __CH32V30x_DAC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* DAC Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t DAC_Trigger; /* Specifies the external trigger for the selected DAC channel.
|
||||||
|
This parameter can be a value of @ref DAC_trigger_selection */
|
||||||
|
|
||||||
|
uint32_t DAC_WaveGeneration; /* Specifies whether DAC channel noise waves or triangle waves
|
||||||
|
are generated, or whether no wave is generated.
|
||||||
|
This parameter can be a value of @ref DAC_wave_generation */
|
||||||
|
|
||||||
|
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or
|
||||||
|
the maximum amplitude triangle generation for the DAC channel.
|
||||||
|
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||||
|
|
||||||
|
uint32_t DAC_OutputBuffer; /* Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref DAC_output_buffer */
|
||||||
|
}DAC_InitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/* DAC_trigger_selection */
|
||||||
|
#define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register
|
||||||
|
has been loaded, and not by external trigger */
|
||||||
|
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||||
|
only in High-density devices*/
|
||||||
|
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */
|
||||||
|
|
||||||
|
/* DAC_wave_generation */
|
||||||
|
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||||
|
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||||
|
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||||
|
|
||||||
|
|
||||||
|
/* DAC_lfsrunmask_triangleamplitude */
|
||||||
|
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||||
|
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */
|
||||||
|
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */
|
||||||
|
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */
|
||||||
|
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */
|
||||||
|
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */
|
||||||
|
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */
|
||||||
|
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */
|
||||||
|
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */
|
||||||
|
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */
|
||||||
|
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */
|
||||||
|
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */
|
||||||
|
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */
|
||||||
|
|
||||||
|
/* DAC_output_buffer */
|
||||||
|
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||||
|
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
||||||
|
|
||||||
|
/* DAC_Channel_selection */
|
||||||
|
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||||
|
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||||
|
|
||||||
|
/* DAC_data_alignment */
|
||||||
|
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||||
|
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||||
|
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||||
|
|
||||||
|
/* DAC_wave_generation */
|
||||||
|
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||||
|
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||||
|
|
||||||
|
|
||||||
|
void DAC_DeInit(void);
|
||||||
|
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||||
|
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||||
|
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||||
|
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||||
|
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||||
|
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||||
|
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||||
|
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||||
|
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
||||||
|
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||||
|
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
@@ -0,0 +1,60 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dbgmcu.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* DBGMCU firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_DBGMCU_H
|
||||||
|
#define __CH32V30x_DBGMCU_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||||
|
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||||
|
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||||
|
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
|
||||||
|
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
|
||||||
|
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400)
|
||||||
|
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800)
|
||||||
|
#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000)
|
||||||
|
#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000)
|
||||||
|
#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000)
|
||||||
|
#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000)
|
||||||
|
#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000)
|
||||||
|
#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000)
|
||||||
|
#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000)
|
||||||
|
#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000)
|
||||||
|
#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000)
|
||||||
|
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
|
||||||
|
#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000)
|
||||||
|
#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000)
|
||||||
|
|
||||||
|
uint32_t DBGMCU_GetREVID(void);
|
||||||
|
uint32_t DBGMCU_GetDEVID(void);
|
||||||
|
uint32_t __get_DEBUG_CR(void);
|
||||||
|
void __set_DEBUG_CR(uint32_t value);
|
||||||
|
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||||
|
uint32_t DBGMCU_GetCHIPID( void );
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,270 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dma.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* DMA firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_DMA_H
|
||||||
|
#define __CH32V30x_DMA_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* DMA Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
|
||||||
|
|
||||||
|
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
|
||||||
|
|
||||||
|
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
|
||||||
|
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||||
|
|
||||||
|
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
|
||||||
|
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||||
|
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||||
|
|
||||||
|
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
|
||||||
|
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||||
|
|
||||||
|
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
|
||||||
|
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||||
|
|
||||||
|
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
|
||||||
|
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||||
|
|
||||||
|
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
|
||||||
|
This parameter can be a value of @ref DMA_memory_data_size */
|
||||||
|
|
||||||
|
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
|
||||||
|
This parameter can be a value of @ref DMA_circular_normal_mode.
|
||||||
|
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||||
|
data transfer is configured on the selected Channel */
|
||||||
|
|
||||||
|
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
|
||||||
|
This parameter can be a value of @ref DMA_priority_level */
|
||||||
|
|
||||||
|
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||||
|
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||||
|
}DMA_InitTypeDef;
|
||||||
|
|
||||||
|
/* DMA_data_transfer_direction */
|
||||||
|
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
||||||
|
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_peripheral_incremented_mode */
|
||||||
|
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
||||||
|
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_memory_incremented_mode */
|
||||||
|
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
||||||
|
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_peripheral_data_size */
|
||||||
|
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||||
|
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
||||||
|
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
||||||
|
|
||||||
|
/* DMA_memory_data_size */
|
||||||
|
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||||
|
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||||
|
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||||
|
|
||||||
|
/* DMA_circular_normal_mode */
|
||||||
|
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
||||||
|
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_priority_level */
|
||||||
|
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
||||||
|
#define DMA_Priority_High ((uint32_t)0x00002000)
|
||||||
|
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
||||||
|
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_memory_to_memory */
|
||||||
|
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
||||||
|
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_interrupts_definition */
|
||||||
|
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||||
|
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||||
|
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||||
|
|
||||||
|
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||||
|
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||||
|
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||||
|
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||||
|
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||||
|
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||||
|
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||||
|
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||||
|
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||||
|
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||||
|
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||||
|
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||||
|
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||||
|
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||||
|
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||||
|
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||||
|
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||||
|
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||||
|
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||||
|
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||||
|
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||||
|
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||||
|
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||||
|
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||||
|
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||||
|
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||||
|
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||||
|
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||||
|
|
||||||
|
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||||
|
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||||
|
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||||
|
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||||
|
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||||
|
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||||
|
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||||
|
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||||
|
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||||
|
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||||
|
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||||
|
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||||
|
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||||
|
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||||
|
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||||
|
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||||
|
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||||
|
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||||
|
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||||
|
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||||
|
#define DMA2_IT_GL6 ((uint32_t)0x10100000)
|
||||||
|
#define DMA2_IT_TC6 ((uint32_t)0x10200000)
|
||||||
|
#define DMA2_IT_HT6 ((uint32_t)0x10400000)
|
||||||
|
#define DMA2_IT_TE6 ((uint32_t)0x10800000)
|
||||||
|
#define DMA2_IT_GL7 ((uint32_t)0x11000000)
|
||||||
|
#define DMA2_IT_TC7 ((uint32_t)0x12000000)
|
||||||
|
#define DMA2_IT_HT7 ((uint32_t)0x14000000)
|
||||||
|
#define DMA2_IT_TE7 ((uint32_t)0x18000000)
|
||||||
|
|
||||||
|
#define DMA2_IT_GL8 ((uint32_t)0x20000001)
|
||||||
|
#define DMA2_IT_TC8 ((uint32_t)0x20000002)
|
||||||
|
#define DMA2_IT_HT8 ((uint32_t)0x20000004)
|
||||||
|
#define DMA2_IT_TE8 ((uint32_t)0x20000008)
|
||||||
|
#define DMA2_IT_GL9 ((uint32_t)0x20000010)
|
||||||
|
#define DMA2_IT_TC9 ((uint32_t)0x20000020)
|
||||||
|
#define DMA2_IT_HT9 ((uint32_t)0x20000040)
|
||||||
|
#define DMA2_IT_TE9 ((uint32_t)0x20000080)
|
||||||
|
#define DMA2_IT_GL10 ((uint32_t)0x20000100)
|
||||||
|
#define DMA2_IT_TC10 ((uint32_t)0x20000200)
|
||||||
|
#define DMA2_IT_HT10 ((uint32_t)0x20000400)
|
||||||
|
#define DMA2_IT_TE10 ((uint32_t)0x20000800)
|
||||||
|
#define DMA2_IT_GL11 ((uint32_t)0x20001000)
|
||||||
|
#define DMA2_IT_TC11 ((uint32_t)0x20002000)
|
||||||
|
#define DMA2_IT_HT11 ((uint32_t)0x20004000)
|
||||||
|
#define DMA2_IT_TE11 ((uint32_t)0x20008000)
|
||||||
|
|
||||||
|
/* DMA_flags_definition */
|
||||||
|
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||||
|
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||||
|
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||||
|
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||||
|
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||||
|
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||||
|
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||||
|
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||||
|
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||||
|
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||||
|
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||||
|
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||||
|
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||||
|
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||||
|
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||||
|
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||||
|
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||||
|
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||||
|
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||||
|
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||||
|
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||||
|
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||||
|
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||||
|
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||||
|
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||||
|
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||||
|
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||||
|
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||||
|
|
||||||
|
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||||
|
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||||
|
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||||
|
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||||
|
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||||
|
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||||
|
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||||
|
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||||
|
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||||
|
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||||
|
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||||
|
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||||
|
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||||
|
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||||
|
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||||
|
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||||
|
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||||
|
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||||
|
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||||
|
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||||
|
#define DMA2_FLAG_GL6 ((uint32_t)0x10100000)
|
||||||
|
#define DMA2_FLAG_TC6 ((uint32_t)0x10200000)
|
||||||
|
#define DMA2_FLAG_HT6 ((uint32_t)0x10400000)
|
||||||
|
#define DMA2_FLAG_TE6 ((uint32_t)0x10800000)
|
||||||
|
#define DMA2_FLAG_GL7 ((uint32_t)0x11000000)
|
||||||
|
#define DMA2_FLAG_TC7 ((uint32_t)0x12000000)
|
||||||
|
#define DMA2_FLAG_HT7 ((uint32_t)0x14000000)
|
||||||
|
#define DMA2_FLAG_TE7 ((uint32_t)0x18000000)
|
||||||
|
|
||||||
|
#define DMA2_FLAG_GL8 ((uint32_t)0x20000001)
|
||||||
|
#define DMA2_FLAG_TC8 ((uint32_t)0x20000002)
|
||||||
|
#define DMA2_FLAG_HT8 ((uint32_t)0x20000004)
|
||||||
|
#define DMA2_FLAG_TE8 ((uint32_t)0x20000008)
|
||||||
|
#define DMA2_FLAG_GL9 ((uint32_t)0x20000010)
|
||||||
|
#define DMA2_FLAG_TC9 ((uint32_t)0x20000020)
|
||||||
|
#define DMA2_FLAG_HT9 ((uint32_t)0x20000040)
|
||||||
|
#define DMA2_FLAG_TE9 ((uint32_t)0x20000080)
|
||||||
|
#define DMA2_FLAG_GL10 ((uint32_t)0x20000100)
|
||||||
|
#define DMA2_FLAG_TC10 ((uint32_t)0x20000200)
|
||||||
|
#define DMA2_FLAG_HT10 ((uint32_t)0x20000400)
|
||||||
|
#define DMA2_FLAG_TE10 ((uint32_t)0x20000800)
|
||||||
|
#define DMA2_FLAG_GL11 ((uint32_t)0x20001000)
|
||||||
|
#define DMA2_FLAG_TC11 ((uint32_t)0x20002000)
|
||||||
|
#define DMA2_FLAG_HT11 ((uint32_t)0x20004000)
|
||||||
|
#define DMA2_FLAG_TE11 ((uint32_t)0x20008000)
|
||||||
|
|
||||||
|
|
||||||
|
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||||
|
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||||
|
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||||
|
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||||
|
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||||
|
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||||
|
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||||
|
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||||
|
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||||
|
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||||
|
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
@@ -0,0 +1,69 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dvp.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* DVP firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_DVP_H
|
||||||
|
#define __CH32V30x_DVP_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* DVP Data Mode */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
Video_Mode = 0,
|
||||||
|
JPEG_Mode,
|
||||||
|
}DVP_Data_ModeTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/* DVP DMA */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DVP_DMA_Disable = 0,
|
||||||
|
DVP_DMA_Enable,
|
||||||
|
}DVP_DMATypeDef;
|
||||||
|
|
||||||
|
/* DVP FLAG and FIFO Reset */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DVP_FLAG_FIFO_RESET_Disable = 0,
|
||||||
|
DVP_FLAG_FIFO_RESET_Enable,
|
||||||
|
}DVP_FLAG_FIFO_RESETTypeDef;
|
||||||
|
|
||||||
|
/* DVP RX Reset */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DVP_RX_RESET_Disable = 0,
|
||||||
|
DVP_RX_RESET_Enable,
|
||||||
|
}DVP_RX_RESETTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void DVP_INTCfg( uint8_t s, uint8_t i );
|
||||||
|
void DVP_Mode( uint8_t s, DVP_Data_ModeTypeDef i);
|
||||||
|
void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,92 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_exti.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* EXTI firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_EXTI_H
|
||||||
|
#define __CH32V30x_EXTI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* EXTI mode enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
EXTI_Mode_Interrupt = 0x00,
|
||||||
|
EXTI_Mode_Event = 0x04
|
||||||
|
}EXTIMode_TypeDef;
|
||||||
|
|
||||||
|
/* EXTI Trigger enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
EXTI_Trigger_Rising = 0x08,
|
||||||
|
EXTI_Trigger_Falling = 0x0C,
|
||||||
|
EXTI_Trigger_Rising_Falling = 0x10
|
||||||
|
}EXTITrigger_TypeDef;
|
||||||
|
|
||||||
|
/* EXTI Init Structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
|
||||||
|
This parameter can be any combination of @ref EXTI_Lines */
|
||||||
|
|
||||||
|
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
|
||||||
|
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||||
|
|
||||||
|
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
|
||||||
|
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||||
|
|
||||||
|
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
|
||||||
|
This parameter can be set either to ENABLE or DISABLE */
|
||||||
|
}EXTI_InitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/* EXTI_Lines */
|
||||||
|
#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
|
||||||
|
#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
|
||||||
|
#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
|
||||||
|
#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
|
||||||
|
#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
|
||||||
|
#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
|
||||||
|
#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
|
||||||
|
#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
|
||||||
|
#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */
|
||||||
|
#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */
|
||||||
|
#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */
|
||||||
|
#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */
|
||||||
|
#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */
|
||||||
|
#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */
|
||||||
|
#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */
|
||||||
|
#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
|
||||||
|
#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */
|
||||||
|
#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */
|
||||||
|
#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD/USBFS OTG
|
||||||
|
Wakeup from suspend event */
|
||||||
|
#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||||
|
#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */
|
||||||
|
|
||||||
|
void EXTI_DeInit(void);
|
||||||
|
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||||
|
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||||
|
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||||
|
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||||
|
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||||
|
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||||
|
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
@@ -0,0 +1,148 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_flash.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/05/24
|
||||||
|
* Description : This file contains all the functions prototypes for the FLASH
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_FLASH_H
|
||||||
|
#define __CH32V30x_FLASH_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* FLASH Status */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
FLASH_BUSY = 1,
|
||||||
|
FLASH_ERROR_PG,
|
||||||
|
FLASH_ERROR_WRP,
|
||||||
|
FLASH_COMPLETE,
|
||||||
|
FLASH_TIMEOUT,
|
||||||
|
FLASH_OP_RANGE_ERROR = 0xFD,
|
||||||
|
FLASH_ALIGN_ERROR = 0xFE,
|
||||||
|
FLASH_ADR_RANGE_ERROR = 0xFF,
|
||||||
|
}FLASH_Status;
|
||||||
|
|
||||||
|
|
||||||
|
/* Write Protect */
|
||||||
|
#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 16 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 31 to 127 */
|
||||||
|
|
||||||
|
#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
|
||||||
|
|
||||||
|
/* Option_Bytes_IWatchdog */
|
||||||
|
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
|
||||||
|
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
|
||||||
|
|
||||||
|
/* Option_Bytes_nRST_STOP */
|
||||||
|
#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
|
||||||
|
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
|
||||||
|
|
||||||
|
/* Option_Bytes_nRST_STDBY */
|
||||||
|
#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
|
||||||
|
#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
|
||||||
|
|
||||||
|
/* FLASH_Interrupts */
|
||||||
|
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
|
||||||
|
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
|
||||||
|
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
|
||||||
|
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
|
||||||
|
|
||||||
|
/* FLASH_Flags */
|
||||||
|
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
|
||||||
|
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
|
||||||
|
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
|
||||||
|
#define FLASH_FLAG_OPTERR ((uint32_t)0x80000001) /* FLASH Option Byte error flag */
|
||||||
|
|
||||||
|
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
|
||||||
|
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
|
||||||
|
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
|
||||||
|
|
||||||
|
/* FLASH_Access_CLK */
|
||||||
|
#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Access Clock = SYSTEM/2 */
|
||||||
|
#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* FLASH Access Clock = SYSTEM */
|
||||||
|
|
||||||
|
|
||||||
|
/*Functions used for all devices*/
|
||||||
|
void FLASH_Unlock(void);
|
||||||
|
void FLASH_Lock(void);
|
||||||
|
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||||
|
FLASH_Status FLASH_EraseAllPages(void);
|
||||||
|
FLASH_Status FLASH_EraseOptionBytes(void);
|
||||||
|
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||||
|
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||||
|
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||||
|
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors);
|
||||||
|
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
|
||||||
|
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
|
||||||
|
uint32_t FLASH_GetUserOptionByte(void);
|
||||||
|
uint32_t FLASH_GetWriteProtectionOptionByte(void);
|
||||||
|
FlagStatus FLASH_GetReadOutProtectionStatus(void);
|
||||||
|
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||||
|
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||||
|
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||||
|
FLASH_Status FLASH_GetStatus(void);
|
||||||
|
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||||
|
void FLASH_Unlock_Fast(void);
|
||||||
|
void FLASH_Lock_Fast(void);
|
||||||
|
void FLASH_ErasePage_Fast(uint32_t Page_Address);
|
||||||
|
void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
|
||||||
|
void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf);
|
||||||
|
void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK);
|
||||||
|
void FLASH_Enhance_Mode(FunctionalState NewState);
|
||||||
|
|
||||||
|
/* New function used for all devices */
|
||||||
|
void FLASH_UnlockBank1(void);
|
||||||
|
void FLASH_LockBank1(void);
|
||||||
|
FLASH_Status FLASH_EraseAllBank1Pages(void);
|
||||||
|
FLASH_Status FLASH_GetBank1Status(void);
|
||||||
|
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
|
||||||
|
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
|
||||||
|
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
@@ -0,0 +1,268 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_fsmc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.1
|
||||||
|
* Date : 2025/03/06
|
||||||
|
* Description : This file contains all the functions prototypes for the FSMC
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_FSMC_H
|
||||||
|
#define __CH32V30x_FSMC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* FSMC Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_AddressSetupTime; /* Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the address setup time.
|
||||||
|
This parameter can be a value between 0 and 0xF.
|
||||||
|
@note: It is not used with synchronous NOR Flash memories. */
|
||||||
|
|
||||||
|
uint32_t FSMC_AddressHoldTime; /* Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the address hold time.
|
||||||
|
This parameter can be a value between 0 and 0xF.
|
||||||
|
@note: It is not used with synchronous NOR Flash memories.*/
|
||||||
|
|
||||||
|
uint32_t FSMC_DataSetupTime; /* Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the data setup time.
|
||||||
|
This parameter can be a value between 0 and 0xFF.
|
||||||
|
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||||
|
|
||||||
|
uint32_t FSMC_BusTurnAroundDuration; /* Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the bus turnaround.
|
||||||
|
This parameter can be a value between 0 and 0xF.
|
||||||
|
@note: It is only used for multiplexed NOR Flash memories. */
|
||||||
|
|
||||||
|
uint32_t FSMC_CLKDivision; /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||||
|
This parameter can be a value between 1 and 0xF.
|
||||||
|
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||||
|
|
||||||
|
uint32_t FSMC_DataLatency; /* Defines the number of memory clock cycles to issue
|
||||||
|
to the memory before getting the first data.
|
||||||
|
The value of this parameter depends on the memory type as shown below:
|
||||||
|
- It must be set to 0 in case of a CRAM
|
||||||
|
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||||
|
- It may assume a value between 0 and 0xF in NOR Flash memories
|
||||||
|
with synchronous burst mode enable */
|
||||||
|
|
||||||
|
uint32_t FSMC_AccessMode; /* Specifies the asynchronous access mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||||
|
}FSMC_NORSRAMTimingInitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_Bank; /* Specifies the NOR/SRAM memory bank that will be used.
|
||||||
|
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
|
||||||
|
|
||||||
|
uint32_t FSMC_DataAddressMux; /* Specifies whether the address and data values are
|
||||||
|
multiplexed on the databus or not.
|
||||||
|
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
|
||||||
|
|
||||||
|
uint32_t FSMC_MemoryType; /* Specifies the type of external memory attached to
|
||||||
|
the corresponding memory bank.
|
||||||
|
This parameter can be a value of @ref FSMC_Memory_Type */
|
||||||
|
|
||||||
|
uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width.
|
||||||
|
This parameter can be a value of @ref FSMC_Data_Width */
|
||||||
|
|
||||||
|
uint32_t FSMC_BurstAccessMode; /* Enables or disables the burst access mode for Flash memory,
|
||||||
|
valid only with synchronous burst Flash memories.
|
||||||
|
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
|
||||||
|
|
||||||
|
uint32_t FSMC_AsynchronousWait; /* Enables or disables wait signal during asynchronous transfers,
|
||||||
|
valid only with asynchronous Flash memories.
|
||||||
|
This parameter can be a value of @ref FSMC_AsynchronousWait */
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSignalPolarity; /* Specifies the wait signal polarity, valid only when accessing
|
||||||
|
the Flash memory in burst mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSignalActive; /* Specifies if the wait signal is asserted by the memory one
|
||||||
|
clock cycle before the wait state or during the wait state,
|
||||||
|
valid only when accessing memories in burst mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Wait_Timing */
|
||||||
|
|
||||||
|
uint32_t FSMC_WriteOperation; /* Enables or disables the write operation in the selected bank by the FSMC.
|
||||||
|
This parameter can be a value of @ref FSMC_Write_Operation */
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSignal; /* Enables or disables the wait-state insertion via wait
|
||||||
|
signal, valid for Flash memory access in burst mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Wait_Signal */
|
||||||
|
|
||||||
|
uint32_t FSMC_ExtendedMode; /* Enables or disables the extended mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Extended_Mode */
|
||||||
|
|
||||||
|
uint32_t FSMC_WriteBurst; /* Enables or disables the write burst operation.
|
||||||
|
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||||
|
|
||||||
|
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the ExtendedMode is not used*/
|
||||||
|
|
||||||
|
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /* Timing Parameters for write access if the ExtendedMode is used*/
|
||||||
|
}FSMC_NORSRAMInitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_SetupTime; /* Defines the number of HCLK cycles to setup address before
|
||||||
|
the command assertion for NAND-Flash read or write access
|
||||||
|
to common/Attribute or I/O memory space (depending on
|
||||||
|
the memory space timing to be configured).
|
||||||
|
This parameter can be a value between 0 and 0xFF.*/
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSetupTime; /* Defines the minimum number of HCLK cycles to assert the
|
||||||
|
command for NAND-Flash read or write access to
|
||||||
|
common/Attribute or I/O memory space (depending on the
|
||||||
|
memory space timing to be configured).
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
|
||||||
|
uint32_t FSMC_HoldSetupTime; /* Defines the number of HCLK clock cycles to hold address
|
||||||
|
(and data for write access) after the command deassertion
|
||||||
|
for NAND-Flash read or write access to common/Attribute
|
||||||
|
or I/O memory space (depending on the memory space timing
|
||||||
|
to be configured).
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
|
||||||
|
uint32_t FSMC_HiZSetupTime; /* Defines the number of HCLK clock cycles during which the
|
||||||
|
databus is kept in HiZ after the start of a NAND-Flash
|
||||||
|
write access to common/Attribute or I/O memory space (depending
|
||||||
|
on the memory space timing to be configured).
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
}FSMC_NAND_PCCARDTimingInitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_Bank; /* Specifies the NAND memory bank that will be used.
|
||||||
|
This parameter can be a value of @ref FSMC_NAND_Bank */
|
||||||
|
|
||||||
|
uint32_t FSMC_Waitfeature; /* Enables or disables the Wait feature for the NAND Memory Bank.
|
||||||
|
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||||
|
|
||||||
|
uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width.
|
||||||
|
This parameter can be any value of @ref FSMC_Data_Width */
|
||||||
|
|
||||||
|
uint32_t FSMC_ECC; /* Enables or disables the ECC computation.
|
||||||
|
This parameter can be any value of @ref FSMC_ECC */
|
||||||
|
|
||||||
|
uint32_t FSMC_ECCPageSize; /* Defines the page size for the extended ECC.
|
||||||
|
This parameter can be any value of @ref FSMC_ECC_Page_Size */
|
||||||
|
|
||||||
|
uint32_t FSMC_TCLRSetupTime; /* Defines the number of HCLK cycles to configure the
|
||||||
|
delay between CLE low and RE low.
|
||||||
|
This parameter can be a value between 0 and 0xFF. */
|
||||||
|
|
||||||
|
uint32_t FSMC_TARSetupTime; /* Defines the number of HCLK cycles to configure the
|
||||||
|
delay between ALE low and RE low.
|
||||||
|
This parameter can be a number between 0x0 and 0xFF */
|
||||||
|
|
||||||
|
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /* FSMC Common Space Timing */
|
||||||
|
|
||||||
|
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */
|
||||||
|
}FSMC_NANDInitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/* FSMC_NORSRAM_Bank */
|
||||||
|
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* FSMC_NAND_Bank */
|
||||||
|
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
|
||||||
|
|
||||||
|
/* FSMC_Data_Address_Bus_Multiplexing */
|
||||||
|
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
|
||||||
|
|
||||||
|
/* FSMC_Memory_Type */
|
||||||
|
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
|
||||||
|
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
|
||||||
|
|
||||||
|
/* FSMC_Data_Width */
|
||||||
|
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||||
|
|
||||||
|
/* FSMC_Burst_Access_Mode */
|
||||||
|
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
|
||||||
|
|
||||||
|
/* FSMC_AsynchronousWait */
|
||||||
|
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
|
||||||
|
|
||||||
|
/* FSMC_Wait_Signal_Polarity */
|
||||||
|
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
|
||||||
|
|
||||||
|
/* FSMC_Wait_Timing */
|
||||||
|
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
|
||||||
|
|
||||||
|
/* FSMC_Write_Operation */
|
||||||
|
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||||||
|
|
||||||
|
/* FSMC_Wait_Signal */
|
||||||
|
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||||||
|
|
||||||
|
/* FSMC_Extended_Mode */
|
||||||
|
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
|
||||||
|
|
||||||
|
/* FSMC_Write_Burst */
|
||||||
|
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
|
||||||
|
|
||||||
|
/* FSMC_Access_Mode */
|
||||||
|
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
|
||||||
|
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
|
||||||
|
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
|
||||||
|
|
||||||
|
/* FSMC_Wait_feature */
|
||||||
|
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
|
||||||
|
|
||||||
|
/* FSMC_ECC */
|
||||||
|
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
|
||||||
|
|
||||||
|
/* FSMC_ECC_Page_Size */
|
||||||
|
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
|
||||||
|
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
|
||||||
|
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
|
||||||
|
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
|
||||||
|
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
|
||||||
|
|
||||||
|
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||||||
|
|
||||||
|
|
||||||
|
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
|
||||||
|
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
|
||||||
|
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||||
|
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||||
|
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||||
|
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||||
|
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||||
|
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||||
|
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||||
|
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
|
||||||
|
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
@@ -0,0 +1,196 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_gpio.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.1
|
||||||
|
* Date : 2025/04/09
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* GPIO firmware library.
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_GPIO_H
|
||||||
|
#define __CH32V30x_GPIO_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* Output Maximum frequency selection */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
GPIO_Speed_10MHz = 1,
|
||||||
|
GPIO_Speed_2MHz,
|
||||||
|
GPIO_Speed_50MHz
|
||||||
|
}GPIOSpeed_TypeDef;
|
||||||
|
|
||||||
|
/* Configuration Mode enumeration */
|
||||||
|
typedef enum
|
||||||
|
{ GPIO_Mode_AIN = 0x0,
|
||||||
|
GPIO_Mode_IN_FLOATING = 0x04,
|
||||||
|
GPIO_Mode_IPD = 0x28,
|
||||||
|
GPIO_Mode_IPU = 0x48,
|
||||||
|
GPIO_Mode_Out_OD = 0x14,
|
||||||
|
GPIO_Mode_Out_PP = 0x10,
|
||||||
|
GPIO_Mode_AF_OD = 0x1C,
|
||||||
|
GPIO_Mode_AF_PP = 0x18
|
||||||
|
}GPIOMode_TypeDef;
|
||||||
|
|
||||||
|
/* GPIO Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
|
||||||
|
This parameter can be any value of @ref GPIO_pins_define */
|
||||||
|
|
||||||
|
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
|
||||||
|
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||||
|
|
||||||
|
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
|
||||||
|
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||||
|
}GPIO_InitTypeDef;
|
||||||
|
|
||||||
|
/* Bit_SET and Bit_RESET enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
Bit_RESET = 0,
|
||||||
|
Bit_SET
|
||||||
|
}BitAction;
|
||||||
|
|
||||||
|
/* GPIO_pins_define */
|
||||||
|
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||||
|
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||||
|
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||||
|
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||||
|
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||||
|
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||||
|
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||||
|
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||||
|
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||||
|
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||||
|
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||||
|
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||||
|
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||||
|
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||||
|
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||||
|
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||||
|
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||||
|
|
||||||
|
/* GPIO_Remap_define */
|
||||||
|
/* PCFR1 */
|
||||||
|
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */
|
||||||
|
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap1_USART3 ((uint32_t)0x00140020) /* USART3 Partial1 Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
|
||||||
|
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
|
||||||
|
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
|
||||||
|
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
|
||||||
|
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
|
||||||
|
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */
|
||||||
|
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */
|
||||||
|
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||||
|
to TIM2 Internal Trigger 1 for calibration
|
||||||
|
(only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1
|
||||||
|
|
||||||
|
/* PCFR2 */
|
||||||
|
#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */
|
||||||
|
|
||||||
|
|
||||||
|
/* GPIO_Port_Sources */
|
||||||
|
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
|
||||||
|
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
|
||||||
|
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
|
||||||
|
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
|
||||||
|
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
|
||||||
|
|
||||||
|
/* GPIO_Pin_sources */
|
||||||
|
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||||
|
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||||
|
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||||
|
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||||
|
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||||
|
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||||
|
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||||
|
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||||
|
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||||
|
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||||
|
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||||
|
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||||
|
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||||
|
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||||
|
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||||
|
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||||
|
|
||||||
|
/* Ethernet_Media_Interface */
|
||||||
|
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
|
||||||
|
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
|
||||||
|
|
||||||
|
|
||||||
|
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||||
|
void GPIO_AFIODeInit(void);
|
||||||
|
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||||
|
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||||
|
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||||
|
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||||
|
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||||
|
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||||
|
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||||
|
void GPIO_EventOutputCmd(FunctionalState NewState);
|
||||||
|
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
|
||||||
|
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||||
|
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,439 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_i2c.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* I2C firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_I2C_H
|
||||||
|
#define __CH32V30x_I2C_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* I2C Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
|
||||||
|
This parameter must be set to a value lower than 400kHz */
|
||||||
|
|
||||||
|
uint16_t I2C_Mode; /* Specifies the I2C mode.
|
||||||
|
This parameter can be a value of @ref I2C_mode */
|
||||||
|
|
||||||
|
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
|
||||||
|
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||||
|
|
||||||
|
uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
|
||||||
|
This parameter can be a 7-bit or 10-bit address. */
|
||||||
|
|
||||||
|
uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
|
||||||
|
This parameter can be a value of @ref I2C_acknowledgement */
|
||||||
|
|
||||||
|
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
|
||||||
|
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||||
|
}I2C_InitTypeDef;
|
||||||
|
|
||||||
|
/* I2C_mode */
|
||||||
|
#define I2C_Mode_I2C ((uint16_t)0x0000)
|
||||||
|
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
|
||||||
|
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
|
||||||
|
|
||||||
|
/* I2C_duty_cycle_in_fast_mode */
|
||||||
|
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
|
||||||
|
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
|
||||||
|
|
||||||
|
/* I2C_acknowledgement */
|
||||||
|
#define I2C_Ack_Enable ((uint16_t)0x0400)
|
||||||
|
#define I2C_Ack_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* I2C_transfer_direction */
|
||||||
|
#define I2C_Direction_Transmitter ((uint8_t)0x00)
|
||||||
|
#define I2C_Direction_Receiver ((uint8_t)0x01)
|
||||||
|
|
||||||
|
/* I2C_acknowledged_address */
|
||||||
|
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
|
||||||
|
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
|
||||||
|
|
||||||
|
/* I2C_registers */
|
||||||
|
#define I2C_Register_CTLR1 ((uint8_t)0x00)
|
||||||
|
#define I2C_Register_CTLR2 ((uint8_t)0x04)
|
||||||
|
#define I2C_Register_OADDR1 ((uint8_t)0x08)
|
||||||
|
#define I2C_Register_OADDR2 ((uint8_t)0x0C)
|
||||||
|
#define I2C_Register_DATAR ((uint8_t)0x10)
|
||||||
|
#define I2C_Register_STAR1 ((uint8_t)0x14)
|
||||||
|
#define I2C_Register_STAR2 ((uint8_t)0x18)
|
||||||
|
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
|
||||||
|
#define I2C_Register_RTR ((uint8_t)0x20)
|
||||||
|
|
||||||
|
/* I2C_SMBus_alert_pin_level */
|
||||||
|
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
|
||||||
|
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
|
||||||
|
|
||||||
|
/* I2C_PEC_position */
|
||||||
|
#define I2C_PECPosition_Next ((uint16_t)0x0800)
|
||||||
|
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
|
||||||
|
|
||||||
|
/* I2C_NACK_position */
|
||||||
|
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
|
||||||
|
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
|
||||||
|
|
||||||
|
/* I2C_interrupts_definition */
|
||||||
|
#define I2C_IT_BUF ((uint16_t)0x0400)
|
||||||
|
#define I2C_IT_EVT ((uint16_t)0x0200)
|
||||||
|
#define I2C_IT_ERR ((uint16_t)0x0100)
|
||||||
|
|
||||||
|
/* I2C_interrupts_definition */
|
||||||
|
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
|
||||||
|
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
|
||||||
|
#define I2C_IT_PECERR ((uint32_t)0x01001000)
|
||||||
|
#define I2C_IT_OVR ((uint32_t)0x01000800)
|
||||||
|
#define I2C_IT_AF ((uint32_t)0x01000400)
|
||||||
|
#define I2C_IT_ARLO ((uint32_t)0x01000200)
|
||||||
|
#define I2C_IT_BERR ((uint32_t)0x01000100)
|
||||||
|
#define I2C_IT_TXE ((uint32_t)0x06000080)
|
||||||
|
#define I2C_IT_RXNE ((uint32_t)0x06000040)
|
||||||
|
#define I2C_IT_STOPF ((uint32_t)0x02000010)
|
||||||
|
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
|
||||||
|
#define I2C_IT_BTF ((uint32_t)0x02000004)
|
||||||
|
#define I2C_IT_ADDR ((uint32_t)0x02000002)
|
||||||
|
#define I2C_IT_SB ((uint32_t)0x02000001)
|
||||||
|
|
||||||
|
/* SR2 register flags */
|
||||||
|
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
|
||||||
|
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
|
||||||
|
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
|
||||||
|
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
|
||||||
|
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
|
||||||
|
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||||
|
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
|
||||||
|
|
||||||
|
/* SR1 register flags */
|
||||||
|
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
|
||||||
|
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
|
||||||
|
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||||
|
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
|
||||||
|
#define I2C_FLAG_AF ((uint32_t)0x10000400)
|
||||||
|
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
|
||||||
|
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
|
||||||
|
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
|
||||||
|
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
|
||||||
|
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||||
|
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
|
||||||
|
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
|
||||||
|
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
|
||||||
|
#define I2C_FLAG_SB ((uint32_t)0x10000001)
|
||||||
|
|
||||||
|
|
||||||
|
/****************I2C Master Events (Events grouped in order of communication)********************/
|
||||||
|
|
||||||
|
/********************************************************************************************************************
|
||||||
|
* @brief Start communicate
|
||||||
|
*
|
||||||
|
* After master use I2C_GenerateSTART() function sending the START condition,the master
|
||||||
|
* has to wait for event 5(the Start condition has been correctly
|
||||||
|
* released on the I2C bus ).
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
/* EVT5 */
|
||||||
|
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||||
|
|
||||||
|
/********************************************************************************************************************
|
||||||
|
* @brief Address Acknowledge
|
||||||
|
*
|
||||||
|
* When start condition correctly released on the bus(check EVT5), the
|
||||||
|
* master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate
|
||||||
|
* it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges
|
||||||
|
* his address. If an acknowledge is sent on the bus, one of the following events will be set:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
|
||||||
|
* event is set.
|
||||||
|
*
|
||||||
|
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
|
||||||
|
* is set
|
||||||
|
*
|
||||||
|
* 3) In case of 10-Bit addressing mode, the master (after generating the START
|
||||||
|
* and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode.
|
||||||
|
* Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent
|
||||||
|
* on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part
|
||||||
|
* of the 10-bit address (LSB) . Then master should wait for event 6.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* EVT6 */
|
||||||
|
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||||
|
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||||
|
/*EVT9 */
|
||||||
|
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||||
|
|
||||||
|
/********************************************************************************************************************
|
||||||
|
* @brief Communication events
|
||||||
|
*
|
||||||
|
* If START condition has generated and slave address
|
||||||
|
* been acknowledged. then the master has to check one of the following events for
|
||||||
|
* communication procedures:
|
||||||
|
*
|
||||||
|
* 1) Master Receiver mode: The master has to wait on the event EVT7 then use
|
||||||
|
* I2C_ReceiveData() function to read the data received from the slave .
|
||||||
|
*
|
||||||
|
* 2) Master Transmitter mode: The master use I2C_SendData() function to send data
|
||||||
|
* then to wait on event EVT8 or EVT8_2.
|
||||||
|
* These two events are similar:
|
||||||
|
* - EVT8 means that the data has been written in the data register and is
|
||||||
|
* being shifted out.
|
||||||
|
* - EVT8_2 means that the data has been physically shifted out and output
|
||||||
|
* on the bus.
|
||||||
|
* In most cases, using EVT8 is sufficient for the application.
|
||||||
|
* Using EVT8_2 will leads to a slower communication speed but will more reliable .
|
||||||
|
* EVT8_2 is also more suitable than EVT8 for testing on the last data transmission
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Note:
|
||||||
|
* In case the user software does not guarantee that this event EVT7 is managed before
|
||||||
|
* the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED
|
||||||
|
* and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Master Receive mode */
|
||||||
|
/* EVT7 */
|
||||||
|
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||||
|
|
||||||
|
/* Master Transmitter mode*/
|
||||||
|
/* EVT8 */
|
||||||
|
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||||
|
/* EVT8_2 */
|
||||||
|
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||||
|
|
||||||
|
|
||||||
|
/******************I2C Slave Events (Events grouped in order of communication)******************/
|
||||||
|
|
||||||
|
/********************************************************************************************************************
|
||||||
|
* @brief Start Communicate events
|
||||||
|
*
|
||||||
|
* Wait on one of these events at the start of the communication. It means that
|
||||||
|
* the I2C peripheral detected a start condition of master device generate on the bus.
|
||||||
|
* If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* a) In normal case (only one address managed by the slave), when the address
|
||||||
|
* sent by the master matches the own address of the peripheral (configured by
|
||||||
|
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||||
|
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||||
|
*
|
||||||
|
* b) In case the address sent by the master matches the second address of the
|
||||||
|
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||||
|
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||||
|
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||||
|
*
|
||||||
|
* c) In case the address sent by the master is General Call (address 0x00) and
|
||||||
|
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||||
|
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* EVT1 */
|
||||||
|
/* a) Case of One Single Address managed by the slave */
|
||||||
|
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||||
|
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||||
|
|
||||||
|
/* b) Case of Dual address managed by the slave */
|
||||||
|
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||||
|
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||||
|
|
||||||
|
/* c) Case of General Call enabled for the slave */
|
||||||
|
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||||
|
|
||||||
|
/********************************************************************************************************************
|
||||||
|
* @brief Communication events
|
||||||
|
*
|
||||||
|
* Wait on one of these events when EVT1 has already been checked :
|
||||||
|
*
|
||||||
|
* - Slave Receiver mode:
|
||||||
|
* - EVT2--The device is expecting to receive a data byte .
|
||||||
|
* - EVT4--The device is expecting the end of the communication: master
|
||||||
|
* sends a stop condition and data transmission is stopped.
|
||||||
|
*
|
||||||
|
* - Slave Transmitter mode:
|
||||||
|
* - EVT3--When a byte has been transmitted by the slave and the Master is expecting
|
||||||
|
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
|
||||||
|
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee
|
||||||
|
* the EVT3 is managed before the current byte end of transfer The second one can optionally
|
||||||
|
* be used.
|
||||||
|
* - EVT3_2--When the master sends a NACK to tell slave device that data transmission
|
||||||
|
* shall end . The slave device has to stop sending
|
||||||
|
* data bytes and wait a Stop condition from bus.
|
||||||
|
*
|
||||||
|
* Note:
|
||||||
|
* If the user software does not guarantee that the event 2 is
|
||||||
|
* managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED
|
||||||
|
* and I2C_FLAG_BTF flag at the same time .
|
||||||
|
* In this case the communication will be slower.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Slave Receiver mode*/
|
||||||
|
/* EVT2 */
|
||||||
|
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||||
|
/* EVT4 */
|
||||||
|
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
||||||
|
|
||||||
|
/* Slave Transmitter mode*/
|
||||||
|
/* EVT3 */
|
||||||
|
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||||
|
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||||
|
/*EVT3_2 */
|
||||||
|
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||||
|
|
||||||
|
|
||||||
|
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||||
|
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||||
|
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||||
|
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
|
||||||
|
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
|
||||||
|
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||||
|
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||||
|
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||||
|
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||||
|
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
|
||||||
|
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
|
||||||
|
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
|
||||||
|
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||||
|
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
|
||||||
|
|
||||||
|
|
||||||
|
/*****************************************************************************************
|
||||||
|
*
|
||||||
|
* I2C State Monitoring Functions
|
||||||
|
*
|
||||||
|
****************************************************************************************
|
||||||
|
* This I2C driver provides three different ways for I2C state monitoring
|
||||||
|
* profit the application requirements and constraints:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* a) First way:
|
||||||
|
* Using I2C_CheckEvent() function:
|
||||||
|
* It compares the status registers (STARR1 and STAR2) content to a given event
|
||||||
|
* (can be the combination of more flags).
|
||||||
|
* If the current status registers includes the given flags will return SUCCESS.
|
||||||
|
* and if the current status registers miss flags will returns ERROR.
|
||||||
|
* - When to use:
|
||||||
|
* - This function is suitable for most applications as well as for startup
|
||||||
|
* activity since the events are fully described in the product reference manual
|
||||||
|
* (CH32FV2x-V3xRM).
|
||||||
|
* - It is also suitable for users who need to define their own events.
|
||||||
|
* - Limitations:
|
||||||
|
* - If an error occurs besides to the monitored error,
|
||||||
|
* the I2C_CheckEvent() function may return SUCCESS despite the communication
|
||||||
|
* in corrupted state. it is suggeted to use error interrupts to monitor the error
|
||||||
|
* events and handle them in IRQ handler.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Note:
|
||||||
|
* The following functions are recommended for error management: :
|
||||||
|
* - I2C_ITConfig() main function of configure and enable the error interrupts.
|
||||||
|
* - I2Cx_ER_IRQHandler() will be called when the error interrupt happen.
|
||||||
|
* Where x is the peripheral instance (I2C1, I2C2 ...)
|
||||||
|
* - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions
|
||||||
|
* to determine which error occurred.
|
||||||
|
* - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd()
|
||||||
|
* \ I2C_GenerateStop() will be use to clear the error flag and source,
|
||||||
|
* and return to correct communication status.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* b) Second way:
|
||||||
|
* Using the function to get a single word(uint32_t) composed of status register 1 and register 2.
|
||||||
|
* (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).
|
||||||
|
* - When to use:
|
||||||
|
*
|
||||||
|
* - This function is suitable for the same applications above but it
|
||||||
|
* don't have the limitations of I2C_GetFlagStatus() function .
|
||||||
|
* The returned value could be compared to events already defined in the
|
||||||
|
* library (CH32V30x_i2c.h) or to custom values defined by user.
|
||||||
|
* - This function can be used to monitor the status of multiple flags simultaneously.
|
||||||
|
* - Contrary to the I2C_CheckEvent () function, this function can choose the time to
|
||||||
|
* accept the event according to the user's needs (when all event flags are set and
|
||||||
|
* no other flags are set, or only when the required flags are set)
|
||||||
|
*
|
||||||
|
* - Limitations:
|
||||||
|
* - User may need to define his own events.
|
||||||
|
* - Same remark concerning the error management is applicable for this
|
||||||
|
* function if user decides to check only regular communication flags (and
|
||||||
|
* ignores error flags).
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* c) Third way:
|
||||||
|
* Using the function I2C_GetFlagStatus() get the status of
|
||||||
|
* one single flag .
|
||||||
|
* - When to use:
|
||||||
|
* - This function could be used for specific applications or in debug phase.
|
||||||
|
* - It is suitable when only one flag checking is needed .
|
||||||
|
*
|
||||||
|
* - Limitations:
|
||||||
|
* - Call this function to access the status register. Some flag bits may be cleared.
|
||||||
|
* - Function may need to be called twice or more in order to monitor one single event.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************************************
|
||||||
|
*
|
||||||
|
* a) Basic state monitoring(First way)
|
||||||
|
********************************************************
|
||||||
|
*/
|
||||||
|
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
|
||||||
|
/*********************************************************
|
||||||
|
*
|
||||||
|
* b) Advanced state monitoring(Second way:)
|
||||||
|
********************************************************
|
||||||
|
*/
|
||||||
|
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
||||||
|
/*********************************************************
|
||||||
|
*
|
||||||
|
* c) Flag-based state monitoring(Third way)
|
||||||
|
*********************************************************
|
||||||
|
*/
|
||||||
|
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||||
|
|
||||||
|
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||||
|
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||||
|
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,58 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_iwdg.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* IWDG firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_IWDG_H
|
||||||
|
#define __CH32V30x_IWDG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* IWDG_WriteAccess */
|
||||||
|
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||||
|
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* IWDG_prescaler */
|
||||||
|
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||||
|
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||||
|
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||||
|
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||||
|
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||||
|
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||||
|
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||||
|
|
||||||
|
/* IWDG_Flag */
|
||||||
|
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||||
|
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||||
|
|
||||||
|
|
||||||
|
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||||
|
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||||
|
void IWDG_SetReload(uint16_t Reload);
|
||||||
|
void IWDG_ReloadCounter(void);
|
||||||
|
void IWDG_Enable(void);
|
||||||
|
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,93 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_misc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* miscellaneous firmware library functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30X_MISC_H
|
||||||
|
#define __CH32V30X_MISC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* CSR_INTSYSCR_INEST_definition */
|
||||||
|
#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
|
||||||
|
#define INTSYSCR_INEST_EN_2Level 0x01 /* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) */
|
||||||
|
#define INTSYSCR_INEST_EN_4Level 0x02 /* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) */
|
||||||
|
#define INTSYSCR_INEST_EN_8Level 0x03 /* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) */
|
||||||
|
|
||||||
|
/* Check the configuration of CSR(0x804) in the startup file(.S)
|
||||||
|
* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3)
|
||||||
|
* priority - bit[7:5] - Preemption Priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2)
|
||||||
|
* priority - bit[7:6] - Preemption Priority
|
||||||
|
* bit[5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1)
|
||||||
|
* priority - bit[7] - Preemption Priority
|
||||||
|
* bit[6:5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||||
|
* priority - bit[7:5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef INTSYSCR_INEST
|
||||||
|
#define INTSYSCR_INEST INTSYSCR_INEST_EN_4Level
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* NVIC Init Structure definition
|
||||||
|
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range is 0.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 7.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 3.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 3.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 1.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 7.
|
||||||
|
* NVIC_IRQChannelSubPriority - range range is 0.
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t NVIC_IRQChannel;
|
||||||
|
uint8_t NVIC_IRQChannelPreemptionPriority;
|
||||||
|
uint8_t NVIC_IRQChannelSubPriority;
|
||||||
|
FunctionalState NVIC_IRQChannelCmd;
|
||||||
|
} NVIC_InitTypeDef;
|
||||||
|
|
||||||
|
/* Preemption_Priority_Group */
|
||||||
|
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
|
||||||
|
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
|
||||||
|
#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_2Level)
|
||||||
|
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) */
|
||||||
|
#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_8Level)
|
||||||
|
#define NVIC_PriorityGroup_3 ((uint32_t)0x03) /* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) */
|
||||||
|
#else
|
||||||
|
#define NVIC_PriorityGroup_2 ((uint32_t)0x02) /* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||||
|
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
@@ -0,0 +1,77 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_opa.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* OPA firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_OPA_H
|
||||||
|
#define __CH32V30x_OPA_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
#define OPA_PSEL_OFFSET 3
|
||||||
|
#define OPA_NSEL_OFFSET 2
|
||||||
|
#define OPA_MODE_OFFSET 1
|
||||||
|
|
||||||
|
|
||||||
|
/* OPA member enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
OPA1=0,
|
||||||
|
OPA2,
|
||||||
|
OPA3,
|
||||||
|
OPA4
|
||||||
|
}OPA_Num_TypeDef;
|
||||||
|
|
||||||
|
/* OPA PSEL enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
CHP0=0,
|
||||||
|
CHP1
|
||||||
|
}OPA_PSEL_TypeDef;
|
||||||
|
|
||||||
|
/* OPA NSEL enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
CHN0=0,
|
||||||
|
CHN1
|
||||||
|
}OPA_NSEL_TypeDef;
|
||||||
|
|
||||||
|
/* OPA out channel enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
OUT_IO_OUT0=0,
|
||||||
|
OUT_IO_OUT1
|
||||||
|
}OPA_Mode_TypeDef;
|
||||||
|
|
||||||
|
/* OPA Init Structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */
|
||||||
|
OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */
|
||||||
|
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
|
||||||
|
OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */
|
||||||
|
}OPA_InitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
void OPA_DeInit(void);
|
||||||
|
void OPA_Init(OPA_InitTypeDef* OPA_InitStruct);
|
||||||
|
void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct);
|
||||||
|
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
@@ -0,0 +1,77 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_pwr.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the PWR
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_PWR_H
|
||||||
|
#define __CH32V30x_PWR_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* PVD_detection_level */
|
||||||
|
#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000)
|
||||||
|
#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020)
|
||||||
|
#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040)
|
||||||
|
#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060)
|
||||||
|
#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080)
|
||||||
|
#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0)
|
||||||
|
#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0)
|
||||||
|
#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#define PWR_PVDLevel_2V2 PWR_PVDLevel_MODE0
|
||||||
|
#define PWR_PVDLevel_2V3 PWR_PVDLevel_MODE1
|
||||||
|
#define PWR_PVDLevel_2V4 PWR_PVDLevel_MODE2
|
||||||
|
#define PWR_PVDLevel_2V5 PWR_PVDLevel_MODE3
|
||||||
|
#define PWR_PVDLevel_2V6 PWR_PVDLevel_MODE4
|
||||||
|
#define PWR_PVDLevel_2V7 PWR_PVDLevel_MODE5
|
||||||
|
#define PWR_PVDLevel_2V8 PWR_PVDLevel_MODE6
|
||||||
|
#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE7
|
||||||
|
|
||||||
|
/* Regulator_state_is_STOP_mode */
|
||||||
|
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||||
|
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
|
||||||
|
|
||||||
|
/* STOP_mode_entry */
|
||||||
|
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||||
|
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||||
|
|
||||||
|
/* PWR_Flag */
|
||||||
|
#define PWR_FLAG_WU ((uint32_t)0x00000001)
|
||||||
|
#define PWR_FLAG_SB ((uint32_t)0x00000002)
|
||||||
|
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
|
||||||
|
|
||||||
|
|
||||||
|
void PWR_DeInit(void);
|
||||||
|
void PWR_BackupAccessCmd(FunctionalState NewState);
|
||||||
|
void PWR_PVDCmd(FunctionalState NewState);
|
||||||
|
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||||
|
void PWR_WakeUpPinCmd(FunctionalState NewState);
|
||||||
|
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||||
|
void PWR_EnterSTANDBYMode(void);
|
||||||
|
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||||
|
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||||
|
void PWR_EnterSTANDBYMode_RAM(void);
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_LV(void);
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void);
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void);
|
||||||
|
void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
@@ -0,0 +1,464 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_rcc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file provides all the RCC firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_RCC_H
|
||||||
|
#define __CH32V30x_RCC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* RCC_Exported_Types */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
|
||||||
|
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
|
||||||
|
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
|
||||||
|
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
|
||||||
|
uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
|
||||||
|
}RCC_ClocksTypeDef;
|
||||||
|
|
||||||
|
/* HSE_configuration */
|
||||||
|
#define RCC_HSE_OFF ((uint32_t)0x00000000)
|
||||||
|
#define RCC_HSE_ON ((uint32_t)0x00010000)
|
||||||
|
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
|
||||||
|
|
||||||
|
/* PLL_entry_clock_source */
|
||||||
|
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
#ifdef CH32V30x_D8
|
||||||
|
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
|
||||||
|
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
|
||||||
|
|
||||||
|
#else
|
||||||
|
#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PLL_multiplication_factor */
|
||||||
|
#ifdef CH32V30x_D8
|
||||||
|
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
|
||||||
|
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
|
||||||
|
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
|
||||||
|
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
|
||||||
|
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
|
||||||
|
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
|
||||||
|
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
|
||||||
|
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
|
||||||
|
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
|
||||||
|
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
|
||||||
|
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
|
||||||
|
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
|
||||||
|
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
|
||||||
|
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
|
||||||
|
#define RCC_PLLMul_18 ((uint32_t)0x003C0000)
|
||||||
|
|
||||||
|
#else
|
||||||
|
#define RCC_PLLMul_18_EXTEN ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PLLMul_3_EXTEN ((uint32_t)0x00040000)
|
||||||
|
#define RCC_PLLMul_4_EXTEN ((uint32_t)0x00080000)
|
||||||
|
#define RCC_PLLMul_5_EXTEN ((uint32_t)0x000C0000)
|
||||||
|
#define RCC_PLLMul_6_EXTEN ((uint32_t)0x00100000)
|
||||||
|
#define RCC_PLLMul_7_EXTEN ((uint32_t)0x00140000)
|
||||||
|
#define RCC_PLLMul_8_EXTEN ((uint32_t)0x00180000)
|
||||||
|
#define RCC_PLLMul_9_EXTEN ((uint32_t)0x001C0000)
|
||||||
|
#define RCC_PLLMul_10_EXTEN ((uint32_t)0x00200000)
|
||||||
|
#define RCC_PLLMul_11_EXTEN ((uint32_t)0x00240000)
|
||||||
|
#define RCC_PLLMul_12_EXTEN ((uint32_t)0x00280000)
|
||||||
|
#define RCC_PLLMul_13_EXTEN ((uint32_t)0x002C0000)
|
||||||
|
#define RCC_PLLMul_14_EXTEN ((uint32_t)0x00300000)
|
||||||
|
#define RCC_PLLMul_6_5_EXTEN ((uint32_t)0x00340000)
|
||||||
|
#define RCC_PLLMul_15_EXTEN ((uint32_t)0x00380000)
|
||||||
|
#define RCC_PLLMul_16_EXTEN ((uint32_t)0x003C0000)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PREDIV1_division_factor */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
|
||||||
|
#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
|
||||||
|
#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
|
||||||
|
#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
|
||||||
|
#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
|
||||||
|
#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
|
||||||
|
#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
|
||||||
|
#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
|
||||||
|
#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
|
||||||
|
#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
|
||||||
|
#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
|
||||||
|
#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
|
||||||
|
#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
|
||||||
|
#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
|
||||||
|
#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PREDIV1_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PREDIV2_division_factor */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
|
||||||
|
#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
|
||||||
|
#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
|
||||||
|
#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
|
||||||
|
#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
|
||||||
|
#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
|
||||||
|
#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
|
||||||
|
#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
|
||||||
|
#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
|
||||||
|
#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
|
||||||
|
#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
|
||||||
|
#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
|
||||||
|
#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
|
||||||
|
#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
|
||||||
|
#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PLL2_multiplication_factor */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_PLL2Mul_2_5 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PLL2Mul_12_5 ((uint32_t)0x00000100)
|
||||||
|
#define RCC_PLL2Mul_4 ((uint32_t)0x00000200)
|
||||||
|
#define RCC_PLL2Mul_5 ((uint32_t)0x00000300)
|
||||||
|
#define RCC_PLL2Mul_6 ((uint32_t)0x00000400)
|
||||||
|
#define RCC_PLL2Mul_7 ((uint32_t)0x00000500)
|
||||||
|
#define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
|
||||||
|
#define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
|
||||||
|
#define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
|
||||||
|
#define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
|
||||||
|
#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
|
||||||
|
#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
|
||||||
|
#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
|
||||||
|
#define RCC_PLL2Mul_15 ((uint32_t)0x00000D00)
|
||||||
|
#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
|
||||||
|
#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PLL3_multiplication_factor */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_PLL3Mul_2_5 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PLL3Mul_12_5 ((uint32_t)0x00001000)
|
||||||
|
#define RCC_PLL3Mul_4 ((uint32_t)0x00002000)
|
||||||
|
#define RCC_PLL3Mul_5 ((uint32_t)0x00003000)
|
||||||
|
#define RCC_PLL3Mul_6 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_PLL3Mul_7 ((uint32_t)0x00005000)
|
||||||
|
#define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
|
||||||
|
#define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
|
||||||
|
#define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
|
||||||
|
#define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
|
||||||
|
#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
|
||||||
|
#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
|
||||||
|
#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
|
||||||
|
#define RCC_PLL3Mul_15 ((uint32_t)0x0000D000)
|
||||||
|
#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
|
||||||
|
#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* System_clock_source */
|
||||||
|
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||||
|
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||||
|
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||||
|
|
||||||
|
/* AHB_clock_source */
|
||||||
|
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
|
||||||
|
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
|
||||||
|
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
|
||||||
|
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||||
|
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
|
||||||
|
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
|
||||||
|
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
|
||||||
|
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
|
||||||
|
|
||||||
|
/* APB1_APB2_clock_source */
|
||||||
|
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
|
||||||
|
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
|
||||||
|
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
|
||||||
|
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
|
||||||
|
|
||||||
|
/* RCC_Interrupt_source */
|
||||||
|
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||||
|
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||||
|
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||||
|
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||||
|
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||||
|
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||||
|
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_IT_PLL2RDY ((uint8_t)0x20)
|
||||||
|
#define RCC_IT_PLL3RDY ((uint8_t)0x40)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USBFS_clock_source */
|
||||||
|
#define RCC_USBFSCLKSource_PLLCLK_Div1 ((uint8_t)0x00)
|
||||||
|
#define RCC_USBFSCLKSource_PLLCLK_Div2 ((uint8_t)0x01)
|
||||||
|
#define RCC_USBFSCLKSource_PLLCLK_Div3 ((uint8_t)0x02)
|
||||||
|
|
||||||
|
#define RCC_OTGFSCLKSource_PLLCLK_Div1 RCC_USBFSCLKSource_PLLCLK_Div1
|
||||||
|
#define RCC_OTGFSCLKSource_PLLCLK_Div2 RCC_USBFSCLKSource_PLLCLK_Div2
|
||||||
|
#define RCC_OTGFSCLKSource_PLLCLK_Div3 RCC_USBFSCLKSource_PLLCLK_Div3
|
||||||
|
|
||||||
|
/* I2S2_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
|
||||||
|
#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* I2S3_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
|
||||||
|
#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ADC_clock_source */
|
||||||
|
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
|
||||||
|
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
|
||||||
|
|
||||||
|
/* LSE_configuration */
|
||||||
|
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||||
|
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||||
|
#define RCC_LSE_Bypass ((uint8_t)0x04)
|
||||||
|
|
||||||
|
/* RTC_clock_source */
|
||||||
|
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
|
||||||
|
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
|
||||||
|
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
|
||||||
|
|
||||||
|
/* AHB_peripheral */
|
||||||
|
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
|
||||||
|
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
|
||||||
|
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
|
||||||
|
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
|
||||||
|
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
|
||||||
|
#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200)
|
||||||
|
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
|
||||||
|
#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800)
|
||||||
|
#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000)
|
||||||
|
#define RCC_AHBPeriph_DVP ((uint32_t)0x00002000)
|
||||||
|
#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
|
||||||
|
#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
|
||||||
|
#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
|
||||||
|
#define RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_USBFS
|
||||||
|
|
||||||
|
/* APB2_peripheral */
|
||||||
|
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
|
||||||
|
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
|
||||||
|
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
|
||||||
|
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
|
||||||
|
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
|
||||||
|
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
|
||||||
|
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
|
||||||
|
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
|
||||||
|
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
|
||||||
|
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||||
|
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
|
||||||
|
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
|
||||||
|
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
|
||||||
|
|
||||||
|
/* APB1_peripheral */
|
||||||
|
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||||
|
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||||
|
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||||
|
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
|
||||||
|
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||||
|
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||||
|
#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040)
|
||||||
|
#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080)
|
||||||
|
#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100)
|
||||||
|
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||||
|
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
|
||||||
|
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||||
|
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||||
|
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||||
|
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||||
|
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||||
|
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||||
|
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
|
||||||
|
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||||
|
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
|
||||||
|
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
|
||||||
|
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||||
|
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||||
|
|
||||||
|
/* Clock_source_to_output_on_MCO_pin */
|
||||||
|
#define RCC_MCO_NoClock ((uint8_t)0x00)
|
||||||
|
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
|
||||||
|
#define RCC_MCO_HSI ((uint8_t)0x05)
|
||||||
|
#define RCC_MCO_HSE ((uint8_t)0x06)
|
||||||
|
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
|
||||||
|
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_MCO_PLL2CLK ((uint8_t)0x08)
|
||||||
|
#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
|
||||||
|
#define RCC_MCO_XT1 ((uint8_t)0x0A)
|
||||||
|
#define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* RCC_Flag */
|
||||||
|
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||||
|
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||||
|
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||||
|
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
|
||||||
|
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||||
|
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||||
|
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||||
|
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||||
|
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||||
|
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||||
|
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||||
|
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
|
||||||
|
#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* SysTick_clock_source */
|
||||||
|
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||||
|
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||||
|
|
||||||
|
/* RNG_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00)
|
||||||
|
#define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ETH1G_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00)
|
||||||
|
#define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01)
|
||||||
|
#define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USBFS_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_USBPLL_Div1 ((uint32_t)0x00)
|
||||||
|
#define RCC_USBPLL_Div2 ((uint32_t)0x01)
|
||||||
|
#define RCC_USBPLL_Div3 ((uint32_t)0x02)
|
||||||
|
#define RCC_USBPLL_Div4 ((uint32_t)0x03)
|
||||||
|
#define RCC_USBPLL_Div5 ((uint32_t)0x04)
|
||||||
|
#define RCC_USBPLL_Div6 ((uint32_t)0x05)
|
||||||
|
#define RCC_USBPLL_Div7 ((uint32_t)0x06)
|
||||||
|
#define RCC_USBPLL_Div8 ((uint32_t)0x07)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USBHSPLL_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_HSBHSPLLCLKSource_HSE ((uint32_t)0x00)
|
||||||
|
#define RCC_HSBHSPLLCLKSource_HSI ((uint32_t)0x01)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USBHSPLLCKREF_clock_select */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_USBHSPLLCKREFCLK_3M ((uint32_t)0x00)
|
||||||
|
#define RCC_USBHSPLLCKREFCLK_4M ((uint32_t)0x01)
|
||||||
|
#define RCC_USBHSPLLCKREFCLK_8M ((uint32_t)0x02)
|
||||||
|
#define RCC_USBHSPLLCKREFCLK_5M ((uint32_t)0x03)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* OTGUSBCLK48M_clock_source */
|
||||||
|
#define RCC_USBCLK48MCLKSource_PLLCLK ((uint32_t)0x00)
|
||||||
|
#define RCC_USBCLK48MCLKSource_USBPHY ((uint32_t)0x01)
|
||||||
|
|
||||||
|
|
||||||
|
void RCC_DeInit(void);
|
||||||
|
void RCC_HSEConfig(uint32_t RCC_HSE);
|
||||||
|
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||||
|
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||||
|
void RCC_HSICmd(FunctionalState NewState);
|
||||||
|
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||||||
|
void RCC_PLLCmd(FunctionalState NewState);
|
||||||
|
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||||
|
uint8_t RCC_GetSYSCLKSource(void);
|
||||||
|
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||||
|
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||||
|
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||||
|
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||||
|
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
|
||||||
|
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||||
|
void RCC_LSICmd(FunctionalState NewState);
|
||||||
|
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||||
|
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||||
|
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||||
|
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||||
|
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||||
|
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||||
|
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||||
|
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||||
|
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||||
|
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||||
|
void RCC_MCOConfig(uint8_t RCC_MCO);
|
||||||
|
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||||
|
void RCC_ClearFlag(void);
|
||||||
|
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||||
|
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||||
|
void RCC_ADCCLKADJcmd(FunctionalState NewState);
|
||||||
|
void RCC_USBFSCLKConfig(uint32_t RCC_USBFSCLKSource);
|
||||||
|
void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource);
|
||||||
|
#define RCC_OTGFSCLKConfig RCC_USBFSCLKConfig
|
||||||
|
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
|
||||||
|
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
|
||||||
|
void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
|
||||||
|
void RCC_PLL2Cmd(FunctionalState NewState);
|
||||||
|
void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
|
||||||
|
void RCC_PLL3Cmd(FunctionalState NewState);
|
||||||
|
void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
|
||||||
|
void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
|
||||||
|
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||||
|
void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource);
|
||||||
|
void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource);
|
||||||
|
void RCC_ETH1G_125Mcmd(FunctionalState NewState);
|
||||||
|
void RCC_USBHSConfig(uint32_t RCC_USBHS);
|
||||||
|
void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource);
|
||||||
|
void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource);
|
||||||
|
void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,43 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_rng.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* RNG firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_RNG_H
|
||||||
|
#define __CH32V30x_RNG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* RNG_flags_definition*/
|
||||||
|
#define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */
|
||||||
|
#define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */
|
||||||
|
#define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */
|
||||||
|
|
||||||
|
/* RNG_interrupts_definition */
|
||||||
|
#define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */
|
||||||
|
#define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */
|
||||||
|
|
||||||
|
|
||||||
|
void RNG_Cmd(FunctionalState NewState);
|
||||||
|
uint32_t RNG_GetRandomNumber(void);
|
||||||
|
void RNG_ITConfig(FunctionalState NewState);
|
||||||
|
FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
|
||||||
|
void RNG_ClearFlag(uint8_t RNG_FLAG);
|
||||||
|
ITStatus RNG_GetITStatus(uint8_t RNG_IT);
|
||||||
|
void RNG_ClearITPendingBit(uint8_t RNG_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
@@ -0,0 +1,56 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_rtc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the RTC
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_RTC_H
|
||||||
|
#define __CH32V30x_RTC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* RTC_interrupts_define */
|
||||||
|
#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */
|
||||||
|
#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */
|
||||||
|
#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */
|
||||||
|
|
||||||
|
/* RTC_interrupts_flags */
|
||||||
|
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */
|
||||||
|
#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */
|
||||||
|
#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */
|
||||||
|
#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */
|
||||||
|
#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */
|
||||||
|
|
||||||
|
|
||||||
|
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
|
||||||
|
void RTC_EnterConfigMode(void);
|
||||||
|
void RTC_ExitConfigMode(void);
|
||||||
|
uint32_t RTC_GetCounter(void);
|
||||||
|
void RTC_SetCounter(uint32_t CounterValue);
|
||||||
|
void RTC_SetPrescaler(uint32_t PrescalerValue);
|
||||||
|
void RTC_SetAlarm(uint32_t AlarmValue);
|
||||||
|
uint32_t RTC_GetDivider(void);
|
||||||
|
void RTC_WaitForLastTask(void);
|
||||||
|
void RTC_WaitForSynchro(void);
|
||||||
|
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
|
||||||
|
void RTC_ClearFlag(uint16_t RTC_FLAG);
|
||||||
|
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
|
||||||
|
void RTC_ClearITPendingBit(uint16_t RTC_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
@@ -0,0 +1,266 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_sdio.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the SDIO
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_SDIO_H
|
||||||
|
#define __CH32V30x_SDIO_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* SDIO Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SDIO_ClockEdge; /* Specifies the clock transition on which the bit capture is made.
|
||||||
|
This parameter can be a value of @ref SDIO_Clock_Edge */
|
||||||
|
|
||||||
|
uint32_t SDIO_ClockBypass; /* Specifies whether the SDIO Clock divider bypass is
|
||||||
|
enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_Clock_Bypass */
|
||||||
|
|
||||||
|
uint32_t SDIO_ClockPowerSave; /* Specifies whether SDIO Clock output is enabled or
|
||||||
|
disabled when the bus is idle.
|
||||||
|
This parameter can be a value of @ref SDIO_Clock_Power_Save */
|
||||||
|
|
||||||
|
uint32_t SDIO_BusWide; /* Specifies the SDIO bus width.
|
||||||
|
This parameter can be a value of @ref SDIO_Bus_Wide */
|
||||||
|
|
||||||
|
uint32_t SDIO_HardwareFlowControl; /* Specifies whether the SDIO hardware flow control is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
|
||||||
|
|
||||||
|
uint8_t SDIO_ClockDiv; /* Specifies the clock frequency of the SDIO controller.
|
||||||
|
This parameter can be a value between 0x00 and 0xFF. */
|
||||||
|
|
||||||
|
} SDIO_InitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SDIO_Argument; /* Specifies the SDIO command argument which is sent
|
||||||
|
to a card as part of a command message. If a command
|
||||||
|
contains an argument, it must be loaded into this register
|
||||||
|
before writing the command to the command register */
|
||||||
|
|
||||||
|
uint32_t SDIO_CmdIndex; /* Specifies the SDIO command index. It must be lower than 0x40. */
|
||||||
|
|
||||||
|
uint32_t SDIO_Response; /* Specifies the SDIO response type.
|
||||||
|
This parameter can be a value of @ref SDIO_Response_Type */
|
||||||
|
|
||||||
|
uint32_t SDIO_Wait; /* Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
|
||||||
|
|
||||||
|
uint32_t SDIO_CPSM; /* Specifies whether SDIO Command path state machine (CPSM)
|
||||||
|
is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_CPSM_State */
|
||||||
|
} SDIO_CmdInitTypeDef;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SDIO_DataTimeOut; /* Specifies the data timeout period in card bus clock periods. */
|
||||||
|
|
||||||
|
uint32_t SDIO_DataLength; /* Specifies the number of data bytes to be transferred. */
|
||||||
|
|
||||||
|
uint32_t SDIO_DataBlockSize; /* Specifies the data block size for block transfer.
|
||||||
|
This parameter can be a value of @ref SDIO_Data_Block_Size */
|
||||||
|
|
||||||
|
uint32_t SDIO_TransferDir; /* Specifies the data transfer direction, whether the transfer
|
||||||
|
is a read or write.
|
||||||
|
This parameter can be a value of @ref SDIO_Transfer_Direction */
|
||||||
|
|
||||||
|
uint32_t SDIO_TransferMode; /* Specifies whether data transfer is in stream or block mode.
|
||||||
|
This parameter can be a value of @ref SDIO_Transfer_Type */
|
||||||
|
|
||||||
|
uint32_t SDIO_DPSM; /* Specifies whether SDIO Data path state machine (DPSM)
|
||||||
|
is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_DPSM_State */
|
||||||
|
} SDIO_DataInitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/* SDIO_Clock_Edge */
|
||||||
|
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
|
||||||
|
|
||||||
|
/* SDIO_Clock_Bypass */
|
||||||
|
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
|
||||||
|
|
||||||
|
/* SDIO_Clock_Power_Save */
|
||||||
|
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
|
||||||
|
|
||||||
|
/* SDIO_Bus_Wide */
|
||||||
|
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
|
||||||
|
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
|
||||||
|
|
||||||
|
/* SDIO_Hardware_Flow_Control */
|
||||||
|
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
|
||||||
|
|
||||||
|
/* SDIO_Power_State */
|
||||||
|
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
|
||||||
|
|
||||||
|
/* SDIO_Interrupt_sources */
|
||||||
|
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
|
||||||
|
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
|
||||||
|
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
|
||||||
|
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
|
||||||
|
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
|
||||||
|
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
|
||||||
|
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
|
||||||
|
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
|
||||||
|
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
|
||||||
|
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
|
||||||
|
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
|
||||||
|
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
|
||||||
|
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
|
||||||
|
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
|
||||||
|
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
|
||||||
|
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
|
||||||
|
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
|
||||||
|
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
|
||||||
|
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
|
||||||
|
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
|
||||||
|
|
||||||
|
/* SDIO_Response_Type */
|
||||||
|
#define SDIO_Response_No ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_Response_Short ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_Response_Long ((uint32_t)0x000000C0)
|
||||||
|
|
||||||
|
/* SDIO_Wait_Interrupt_State */
|
||||||
|
#define SDIO_Wait_No ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_Wait_IT ((uint32_t)0x00000100)
|
||||||
|
#define SDIO_Wait_Pend ((uint32_t)0x00000200)
|
||||||
|
|
||||||
|
/* SDIO_CPSM_State */
|
||||||
|
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
|
||||||
|
|
||||||
|
/* SDIO_Response_Registers */
|
||||||
|
#define SDIO_RESP1 ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_RESP2 ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_RESP3 ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_RESP4 ((uint32_t)0x0000000C)
|
||||||
|
|
||||||
|
/* SDIO_Data_Block_Size */
|
||||||
|
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
|
||||||
|
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
|
||||||
|
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
|
||||||
|
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
|
||||||
|
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
|
||||||
|
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
|
||||||
|
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
|
||||||
|
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
|
||||||
|
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
|
||||||
|
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
|
||||||
|
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
|
||||||
|
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
|
||||||
|
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
|
||||||
|
|
||||||
|
/* SDIO_Transfer_Direction */
|
||||||
|
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
|
||||||
|
|
||||||
|
/* SDIO_Transfer_Type */
|
||||||
|
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
|
||||||
|
|
||||||
|
/* SDIO_DPSM_State */
|
||||||
|
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
|
||||||
|
|
||||||
|
/* SDIO_Flags */
|
||||||
|
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
|
||||||
|
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
|
||||||
|
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
|
||||||
|
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
|
||||||
|
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
|
||||||
|
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
|
||||||
|
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
|
||||||
|
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
|
||||||
|
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
|
||||||
|
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
|
||||||
|
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
|
||||||
|
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
|
||||||
|
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
|
||||||
|
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
|
||||||
|
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
|
||||||
|
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
|
||||||
|
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
|
||||||
|
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
|
||||||
|
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
|
||||||
|
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
|
||||||
|
|
||||||
|
/* SDIO_Read_Wait_Mode */
|
||||||
|
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
#define SDIO_DataControl_DTEN ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_DataControl_DTDIR ((uint32_t)0x00000002)
|
||||||
|
#define SDIO_DataControl_DTMODE ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_DataControl_DMAEN ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_DataControl_DBLOCKSIZE ((uint32_t)0x000000F0)
|
||||||
|
#define SDIO_DataControl_RWSTART ((uint32_t)0x00000100)
|
||||||
|
#define SDIO_DataControl_RWSTOP ((uint32_t)0x00000200)
|
||||||
|
#define SDIO_DataControl_RWMOD ((uint32_t)0x00000400)
|
||||||
|
#define SDIO_DataControl_SDIOEN ((uint32_t)0x00000800)
|
||||||
|
|
||||||
|
|
||||||
|
void SDIO_DeInit(void);
|
||||||
|
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||||
|
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||||
|
void SDIO_ClockCmd(FunctionalState NewState);
|
||||||
|
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
|
||||||
|
uint32_t SDIO_GetPowerState(void);
|
||||||
|
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
|
||||||
|
void SDIO_DMACmd(FunctionalState NewState);
|
||||||
|
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
|
||||||
|
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
|
||||||
|
uint8_t SDIO_GetCommandResponse(void);
|
||||||
|
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
|
||||||
|
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||||
|
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||||
|
uint32_t SDIO_GetDataCounter(void);
|
||||||
|
uint32_t SDIO_ReadData(void);
|
||||||
|
void SDIO_WriteData(uint32_t Data);
|
||||||
|
uint32_t SDIO_GetFIFOCount(void);
|
||||||
|
void SDIO_StartSDIOReadWait(FunctionalState NewState);
|
||||||
|
void SDIO_StopSDIOReadWait(FunctionalState NewState);
|
||||||
|
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
|
||||||
|
void SDIO_SetSDIOOperation(FunctionalState NewState);
|
||||||
|
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
|
||||||
|
void SDIO_CommandCompletionCmd(FunctionalState NewState);
|
||||||
|
void SDIO_CEATAITCmd(FunctionalState NewState);
|
||||||
|
void SDIO_SendCEATACmd(FunctionalState NewState);
|
||||||
|
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
|
||||||
|
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
|
||||||
|
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
|
||||||
|
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
@@ -0,0 +1,231 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_spi.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* SPI firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_SPI_H
|
||||||
|
#define __CH32V30x_SPI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* SPI Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
|
||||||
|
This parameter can be a value of @ref SPI_data_direction */
|
||||||
|
|
||||||
|
uint16_t SPI_Mode; /* Specifies the SPI operating mode.
|
||||||
|
This parameter can be a value of @ref SPI_mode */
|
||||||
|
|
||||||
|
uint16_t SPI_DataSize; /* Specifies the SPI data size.
|
||||||
|
This parameter can be a value of @ref SPI_data_size */
|
||||||
|
|
||||||
|
uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
|
||||||
|
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||||
|
|
||||||
|
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
|
||||||
|
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||||
|
|
||||||
|
uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
|
||||||
|
hardware (NSS pin) or by software using the SSI bit.
|
||||||
|
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||||
|
|
||||||
|
uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
|
||||||
|
used to configure the transmit and receive SCK clock.
|
||||||
|
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
|
||||||
|
@note The communication clock is derived from the master
|
||||||
|
clock. The slave clock does not need to be set. */
|
||||||
|
|
||||||
|
uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit.
|
||||||
|
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||||
|
|
||||||
|
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
|
||||||
|
}SPI_InitTypeDef;
|
||||||
|
|
||||||
|
/* I2S Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
|
||||||
|
uint16_t I2S_Mode; /* Specifies the I2S operating mode.
|
||||||
|
This parameter can be a value of @ref I2S_Mode */
|
||||||
|
|
||||||
|
uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Standard */
|
||||||
|
|
||||||
|
uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Data_Format */
|
||||||
|
|
||||||
|
uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not.
|
||||||
|
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||||
|
|
||||||
|
uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||||
|
|
||||||
|
uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock.
|
||||||
|
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||||
|
}I2S_InitTypeDef;
|
||||||
|
|
||||||
|
/* SPI_data_direction */
|
||||||
|
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||||
|
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||||
|
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||||
|
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||||
|
|
||||||
|
/* SPI_mode */
|
||||||
|
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||||
|
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* SPI_data_size */
|
||||||
|
#define SPI_DataSize_16b ((uint16_t)0x0800)
|
||||||
|
#define SPI_DataSize_8b ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* SPI_Clock_Polarity */
|
||||||
|
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||||
|
#define SPI_CPOL_High ((uint16_t)0x0002)
|
||||||
|
|
||||||
|
/* SPI_Clock_Phase */
|
||||||
|
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||||
|
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
/* SPI_Slave_Select_management */
|
||||||
|
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||||
|
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* SPI_BaudRate_Prescaler */
|
||||||
|
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||||
|
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||||
|
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||||
|
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||||
|
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||||
|
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||||
|
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||||
|
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||||
|
|
||||||
|
/* SPI_MSB_LSB_transmission */
|
||||||
|
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||||
|
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
|
||||||
|
|
||||||
|
/* I2S_Mode */
|
||||||
|
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||||
|
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||||
|
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||||
|
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||||
|
|
||||||
|
/* I2S_Standard */
|
||||||
|
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||||
|
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||||
|
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||||
|
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||||
|
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||||
|
|
||||||
|
/* I2S_Data_Format */
|
||||||
|
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||||
|
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||||
|
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||||
|
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||||
|
|
||||||
|
/* I2S_MCLK_Output */
|
||||||
|
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
|
||||||
|
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* I2S_Audio_Frequency */
|
||||||
|
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||||
|
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||||
|
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||||
|
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||||
|
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||||
|
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||||
|
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||||
|
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||||
|
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||||
|
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||||
|
|
||||||
|
/* I2S_Clock_Polarity */
|
||||||
|
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||||
|
#define I2S_CPOL_High ((uint16_t)0x0008)
|
||||||
|
|
||||||
|
/* SPI_I2S_DMA_transfer_requests */
|
||||||
|
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||||
|
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
/* SPI_NSS_internal_software_management */
|
||||||
|
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||||
|
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||||
|
|
||||||
|
/* SPI_CRC_Transmit_Receive */
|
||||||
|
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||||
|
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||||
|
|
||||||
|
/* SPI_direction_transmit_receive */
|
||||||
|
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||||
|
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||||
|
|
||||||
|
/* SPI_I2S_interrupts_definition */
|
||||||
|
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||||
|
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||||
|
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||||
|
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||||
|
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||||
|
#define SPI_IT_CRCERR ((uint8_t)0x54)
|
||||||
|
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||||
|
|
||||||
|
/* SPI_I2S_flags_definition */
|
||||||
|
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||||
|
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||||
|
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
|
||||||
|
#define I2S_FLAG_UDR ((uint16_t)0x0008)
|
||||||
|
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||||
|
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||||
|
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||||
|
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||||
|
|
||||||
|
|
||||||
|
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||||
|
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||||
|
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||||
|
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||||
|
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||||
|
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||||
|
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
|
||||||
|
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||||
|
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||||
|
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||||
|
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||||
|
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||||
|
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||||
|
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||||
|
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,517 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_tim.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* TIM firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_TIM_H
|
||||||
|
#define __CH32V30x_TIM_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* TIM Time Base Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
|
||||||
|
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t TIM_CounterMode; /* Specifies the counter mode.
|
||||||
|
This parameter can be a value of @ref TIM_Counter_Mode */
|
||||||
|
|
||||||
|
uint16_t TIM_Period; /* Specifies the period value to be loaded into the active
|
||||||
|
Auto-Reload Register at the next update event.
|
||||||
|
This parameter must be a number between 0x0000 and 0xFFFF. */
|
||||||
|
|
||||||
|
uint16_t TIM_ClockDivision; /* Specifies the clock division.
|
||||||
|
This parameter can be a value of @ref TIM_Clock_Division_CKD */
|
||||||
|
|
||||||
|
uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter
|
||||||
|
reaches zero, an update event is generated and counting restarts
|
||||||
|
from the RCR value (N).
|
||||||
|
This means in PWM mode that (N+1) corresponds to:
|
||||||
|
- the number of PWM periods in edge-aligned mode
|
||||||
|
- the number of half PWM period in center-aligned mode
|
||||||
|
This parameter must be a number between 0x00 and 0xFF.
|
||||||
|
@note This parameter is valid only for TIM1 and TIM8. */
|
||||||
|
} TIM_TimeBaseInitTypeDef;
|
||||||
|
|
||||||
|
/* TIM Output Compare Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t TIM_OCMode; /* Specifies the TIM mode.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
|
||||||
|
|
||||||
|
uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_state */
|
||||||
|
|
||||||
|
uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_N_state
|
||||||
|
@note This parameter is valid only for TIM1 and TIM8. */
|
||||||
|
|
||||||
|
uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||||
|
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t TIM_OCPolarity; /* Specifies the output polarity.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
|
||||||
|
|
||||||
|
uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
|
||||||
|
@note This parameter is valid only for TIM1 and TIM8. */
|
||||||
|
|
||||||
|
uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
|
||||||
|
@note This parameter is valid only for TIM1 and TIM8. */
|
||||||
|
|
||||||
|
uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
|
||||||
|
@note This parameter is valid only for TIM1 and TIM8. */
|
||||||
|
} TIM_OCInitTypeDef;
|
||||||
|
|
||||||
|
/* TIM Input Capture Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t TIM_Channel; /* Specifies the TIM channel.
|
||||||
|
This parameter can be a value of @ref TIM_Channel */
|
||||||
|
|
||||||
|
uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal.
|
||||||
|
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||||
|
|
||||||
|
uint16_t TIM_ICSelection; /* Specifies the input.
|
||||||
|
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||||
|
|
||||||
|
uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler.
|
||||||
|
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||||
|
|
||||||
|
uint16_t TIM_ICFilter; /* Specifies the input capture filter.
|
||||||
|
This parameter can be a number between 0x0 and 0xF */
|
||||||
|
} TIM_ICInitTypeDef;
|
||||||
|
|
||||||
|
/* BDTR structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode.
|
||||||
|
This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
|
||||||
|
|
||||||
|
uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state.
|
||||||
|
This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||||
|
|
||||||
|
uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters.
|
||||||
|
This parameter can be a value of @ref Lock_level */
|
||||||
|
|
||||||
|
uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the
|
||||||
|
switching-on of the outputs.
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
|
||||||
|
uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not.
|
||||||
|
This parameter can be a value of @ref Break_Input_enable_disable */
|
||||||
|
|
||||||
|
uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity.
|
||||||
|
This parameter can be a value of @ref Break_Polarity */
|
||||||
|
|
||||||
|
uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
|
||||||
|
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||||
|
} TIM_BDTRInitTypeDef;
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_and_PWM_modes */
|
||||||
|
#define TIM_OCMode_Timing ((uint16_t)0x0000)
|
||||||
|
#define TIM_OCMode_Active ((uint16_t)0x0010)
|
||||||
|
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
|
||||||
|
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
|
||||||
|
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
|
||||||
|
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
|
||||||
|
|
||||||
|
/* TIM_One_Pulse_Mode */
|
||||||
|
#define TIM_OPMode_Single ((uint16_t)0x0008)
|
||||||
|
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Channel */
|
||||||
|
#define TIM_Channel_1 ((uint16_t)0x0000)
|
||||||
|
#define TIM_Channel_2 ((uint16_t)0x0004)
|
||||||
|
#define TIM_Channel_3 ((uint16_t)0x0008)
|
||||||
|
#define TIM_Channel_4 ((uint16_t)0x000C)
|
||||||
|
|
||||||
|
/* TIM_Clock_Division_CKD */
|
||||||
|
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
|
||||||
|
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
|
||||||
|
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
|
||||||
|
|
||||||
|
/* TIM_Counter_Mode */
|
||||||
|
#define TIM_CounterMode_Up ((uint16_t)0x0000)
|
||||||
|
#define TIM_CounterMode_Down ((uint16_t)0x0010)
|
||||||
|
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
|
||||||
|
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
|
||||||
|
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_Polarity */
|
||||||
|
#define TIM_OCPolarity_High ((uint16_t)0x0000)
|
||||||
|
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_N_Polarity */
|
||||||
|
#define TIM_OCNPolarity_High ((uint16_t)0x0000)
|
||||||
|
#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_state */
|
||||||
|
#define TIM_OutputState_Disable ((uint16_t)0x0000)
|
||||||
|
#define TIM_OutputState_Enable ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_N_state */
|
||||||
|
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
|
||||||
|
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
|
||||||
|
|
||||||
|
/* TIM_Capture_Compare_state */
|
||||||
|
#define TIM_CCx_Enable ((uint16_t)0x0001)
|
||||||
|
#define TIM_CCx_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Capture_Compare_N_state */
|
||||||
|
#define TIM_CCxN_Enable ((uint16_t)0x0004)
|
||||||
|
#define TIM_CCxN_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* Break_Input_enable_disable */
|
||||||
|
#define TIM_Break_Enable ((uint16_t)0x1000)
|
||||||
|
#define TIM_Break_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* Break_Polarity */
|
||||||
|
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
|
||||||
|
#define TIM_BreakPolarity_High ((uint16_t)0x2000)
|
||||||
|
|
||||||
|
/* TIM_AOE_Bit_Set_Reset */
|
||||||
|
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
|
||||||
|
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* Lock_level */
|
||||||
|
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
|
||||||
|
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
|
||||||
|
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
|
||||||
|
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
|
||||||
|
|
||||||
|
/* OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||||
|
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
|
||||||
|
#define TIM_OSSIState_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* OSSR_Off_State_Selection_for_Run_mode_state */
|
||||||
|
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
|
||||||
|
#define TIM_OSSRState_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_Idle_State */
|
||||||
|
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
|
||||||
|
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_N_Idle_State */
|
||||||
|
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
|
||||||
|
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Input_Capture_Polarity */
|
||||||
|
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
|
||||||
|
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
|
||||||
|
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
|
||||||
|
|
||||||
|
/* TIM_Input_Capture_Selection */
|
||||||
|
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be
|
||||||
|
connected to IC1, IC2, IC3 or IC4, respectively */
|
||||||
|
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be
|
||||||
|
connected to IC2, IC1, IC4 or IC3, respectively. */
|
||||||
|
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
|
||||||
|
|
||||||
|
/* TIM_Input_Capture_Prescaler */
|
||||||
|
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
|
||||||
|
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */
|
||||||
|
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */
|
||||||
|
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */
|
||||||
|
|
||||||
|
/* TIM_interrupt_sources */
|
||||||
|
#define TIM_IT_Update ((uint16_t)0x0001)
|
||||||
|
#define TIM_IT_CC1 ((uint16_t)0x0002)
|
||||||
|
#define TIM_IT_CC2 ((uint16_t)0x0004)
|
||||||
|
#define TIM_IT_CC3 ((uint16_t)0x0008)
|
||||||
|
#define TIM_IT_CC4 ((uint16_t)0x0010)
|
||||||
|
#define TIM_IT_COM ((uint16_t)0x0020)
|
||||||
|
#define TIM_IT_Trigger ((uint16_t)0x0040)
|
||||||
|
#define TIM_IT_Break ((uint16_t)0x0080)
|
||||||
|
|
||||||
|
/* TIM_DMA_Base_address */
|
||||||
|
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
|
||||||
|
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
|
||||||
|
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
|
||||||
|
#define TIM_DMABase_DIER ((uint16_t)0x0003)
|
||||||
|
#define TIM_DMABase_SR ((uint16_t)0x0004)
|
||||||
|
#define TIM_DMABase_EGR ((uint16_t)0x0005)
|
||||||
|
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
|
||||||
|
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
|
||||||
|
#define TIM_DMABase_CCER ((uint16_t)0x0008)
|
||||||
|
#define TIM_DMABase_CNT ((uint16_t)0x0009)
|
||||||
|
#define TIM_DMABase_PSC ((uint16_t)0x000A)
|
||||||
|
#define TIM_DMABase_ARR ((uint16_t)0x000B)
|
||||||
|
#define TIM_DMABase_RCR ((uint16_t)0x000C)
|
||||||
|
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
|
||||||
|
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
|
||||||
|
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
|
||||||
|
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
|
||||||
|
#define TIM_DMABase_BDTR ((uint16_t)0x0011)
|
||||||
|
#define TIM_DMABase_DCR ((uint16_t)0x0012)
|
||||||
|
|
||||||
|
/* TIM_DMA_Burst_Length */
|
||||||
|
#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
|
||||||
|
#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
|
||||||
|
#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
|
||||||
|
#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
|
||||||
|
#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
|
||||||
|
#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
|
||||||
|
#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
|
||||||
|
#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
|
||||||
|
#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
|
||||||
|
#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
|
||||||
|
#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
|
||||||
|
#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
|
||||||
|
#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
|
||||||
|
#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
|
||||||
|
#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
|
||||||
|
#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
|
||||||
|
#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
|
||||||
|
#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
|
||||||
|
|
||||||
|
/* TIM_DMA_sources */
|
||||||
|
#define TIM_DMA_Update ((uint16_t)0x0100)
|
||||||
|
#define TIM_DMA_CC1 ((uint16_t)0x0200)
|
||||||
|
#define TIM_DMA_CC2 ((uint16_t)0x0400)
|
||||||
|
#define TIM_DMA_CC3 ((uint16_t)0x0800)
|
||||||
|
#define TIM_DMA_CC4 ((uint16_t)0x1000)
|
||||||
|
#define TIM_DMA_COM ((uint16_t)0x2000)
|
||||||
|
#define TIM_DMA_Trigger ((uint16_t)0x4000)
|
||||||
|
|
||||||
|
/* TIM_External_Trigger_Prescaler */
|
||||||
|
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
|
||||||
|
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
|
||||||
|
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
|
||||||
|
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
|
||||||
|
|
||||||
|
/* TIM_Internal_Trigger_Selection */
|
||||||
|
#define TIM_TS_ITR0 ((uint16_t)0x0000)
|
||||||
|
#define TIM_TS_ITR1 ((uint16_t)0x0010)
|
||||||
|
#define TIM_TS_ITR2 ((uint16_t)0x0020)
|
||||||
|
#define TIM_TS_ITR3 ((uint16_t)0x0030)
|
||||||
|
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
|
||||||
|
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
|
||||||
|
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
|
||||||
|
#define TIM_TS_ETRF ((uint16_t)0x0070)
|
||||||
|
|
||||||
|
/* TIM_TIx_External_Clock_Source */
|
||||||
|
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
|
||||||
|
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
|
||||||
|
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
|
||||||
|
|
||||||
|
/* TIM_External_Trigger_Polarity */
|
||||||
|
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
|
||||||
|
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Prescaler_Reload_Mode */
|
||||||
|
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
|
||||||
|
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
/* TIM_Forced_Action */
|
||||||
|
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
|
||||||
|
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
|
||||||
|
|
||||||
|
/* TIM_Encoder_Mode */
|
||||||
|
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
|
||||||
|
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
|
||||||
|
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
|
||||||
|
|
||||||
|
/* TIM_Event_Source */
|
||||||
|
#define TIM_EventSource_Update ((uint16_t)0x0001)
|
||||||
|
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
|
||||||
|
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
|
||||||
|
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
|
||||||
|
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
|
||||||
|
#define TIM_EventSource_COM ((uint16_t)0x0020)
|
||||||
|
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
|
||||||
|
#define TIM_EventSource_Break ((uint16_t)0x0080)
|
||||||
|
|
||||||
|
/* TIM_Update_Source */
|
||||||
|
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow
|
||||||
|
or the setting of UG bit, or an update generation
|
||||||
|
through the slave mode controller. */
|
||||||
|
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_Preload_State */
|
||||||
|
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
|
||||||
|
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_Fast_State */
|
||||||
|
#define TIM_OCFast_Enable ((uint16_t)0x0004)
|
||||||
|
#define TIM_OCFast_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_Clear_State */
|
||||||
|
#define TIM_OCClear_Enable ((uint16_t)0x0080)
|
||||||
|
#define TIM_OCClear_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Trigger_Output_Source */
|
||||||
|
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
|
||||||
|
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
|
||||||
|
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
|
||||||
|
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
|
||||||
|
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
|
||||||
|
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
|
||||||
|
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
|
||||||
|
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
|
||||||
|
|
||||||
|
/* TIM_Slave_Mode */
|
||||||
|
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
|
||||||
|
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
|
||||||
|
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
|
||||||
|
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
|
||||||
|
|
||||||
|
/* TIM_Master_Slave_Mode */
|
||||||
|
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
|
||||||
|
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Flags */
|
||||||
|
#define TIM_FLAG_Update ((uint16_t)0x0001)
|
||||||
|
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
|
||||||
|
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
|
||||||
|
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
|
||||||
|
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
|
||||||
|
#define TIM_FLAG_COM ((uint16_t)0x0020)
|
||||||
|
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
|
||||||
|
#define TIM_FLAG_Break ((uint16_t)0x0080)
|
||||||
|
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
|
||||||
|
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
|
||||||
|
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
|
||||||
|
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
|
||||||
|
|
||||||
|
/* TIM_Legacy */
|
||||||
|
#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
|
||||||
|
#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
|
||||||
|
#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
|
||||||
|
#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
|
||||||
|
#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
|
||||||
|
#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
|
||||||
|
#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
|
||||||
|
#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
|
||||||
|
#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
|
||||||
|
#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
|
||||||
|
#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
|
||||||
|
#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
|
||||||
|
#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
|
||||||
|
#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
|
||||||
|
#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
|
||||||
|
#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
|
||||||
|
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
|
||||||
|
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
|
||||||
|
|
||||||
|
|
||||||
|
void TIM_DeInit(TIM_TypeDef* TIMx);
|
||||||
|
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
||||||
|
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||||
|
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||||
|
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||||
|
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||||
|
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||||
|
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||||
|
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
|
||||||
|
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
||||||
|
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||||
|
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||||
|
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
|
||||||
|
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
|
||||||
|
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
|
||||||
|
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
|
||||||
|
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
|
||||||
|
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
|
||||||
|
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
||||||
|
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
|
||||||
|
uint16_t TIM_ICPolarity, uint16_t ICFilter);
|
||||||
|
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||||
|
uint16_t ExtTRGFilter);
|
||||||
|
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
|
||||||
|
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
|
||||||
|
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||||
|
uint16_t ExtTRGFilter);
|
||||||
|
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
|
||||||
|
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
|
||||||
|
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
||||||
|
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
|
||||||
|
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
|
||||||
|
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||||
|
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||||
|
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||||
|
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||||
|
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||||
|
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||||
|
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||||
|
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||||
|
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||||
|
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||||
|
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||||
|
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||||
|
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||||
|
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||||
|
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||||
|
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||||
|
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||||
|
void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
||||||
|
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||||
|
void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
||||||
|
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||||
|
void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
||||||
|
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||||
|
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
|
||||||
|
void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
|
||||||
|
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
|
||||||
|
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
|
||||||
|
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
|
||||||
|
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
|
||||||
|
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
|
||||||
|
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
|
||||||
|
void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
|
||||||
|
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
|
||||||
|
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
|
||||||
|
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
|
||||||
|
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
|
||||||
|
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
|
||||||
|
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||||
|
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||||
|
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||||
|
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||||
|
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
|
||||||
|
uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
|
||||||
|
uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
|
||||||
|
uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
|
||||||
|
uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
|
||||||
|
uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
|
||||||
|
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
|
||||||
|
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
||||||
|
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
||||||
|
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
||||||
|
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,195 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_usart.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* USART firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_USART_H
|
||||||
|
#define __CH32V30x_USART_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* USART Init Structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
|
||||||
|
The baud rate is computed using the following formula:
|
||||||
|
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||||
|
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
|
||||||
|
|
||||||
|
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
|
||||||
|
This parameter can be a value of @ref USART_Word_Length */
|
||||||
|
|
||||||
|
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
|
||||||
|
This parameter can be a value of @ref USART_Stop_Bits */
|
||||||
|
|
||||||
|
uint16_t USART_Parity; /* Specifies the parity mode.
|
||||||
|
This parameter can be a value of @ref USART_Parity
|
||||||
|
@note When parity is enabled, the computed parity is inserted
|
||||||
|
at the MSB position of the transmitted data (9th bit when
|
||||||
|
the word length is set to 9 data bits; 8th bit when the
|
||||||
|
word length is set to 8 data bits). */
|
||||||
|
|
||||||
|
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref USART_Mode */
|
||||||
|
|
||||||
|
uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
|
||||||
|
or disabled.
|
||||||
|
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||||
|
} USART_InitTypeDef;
|
||||||
|
|
||||||
|
/* USART Clock Init Structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
|
||||||
|
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref USART_Clock */
|
||||||
|
|
||||||
|
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
|
||||||
|
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||||
|
|
||||||
|
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
|
||||||
|
This parameter can be a value of @ref USART_Clock_Phase */
|
||||||
|
|
||||||
|
uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
|
||||||
|
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||||
|
This parameter can be a value of @ref USART_Last_Bit */
|
||||||
|
} USART_ClockInitTypeDef;
|
||||||
|
|
||||||
|
/* USART_Word_Length */
|
||||||
|
#define USART_WordLength_8b ((uint16_t)0x0000)
|
||||||
|
#define USART_WordLength_9b ((uint16_t)0x1000)
|
||||||
|
|
||||||
|
/* USART_Stop_Bits */
|
||||||
|
#define USART_StopBits_1 ((uint16_t)0x0000)
|
||||||
|
#define USART_StopBits_0_5 ((uint16_t)0x1000)
|
||||||
|
#define USART_StopBits_2 ((uint16_t)0x2000)
|
||||||
|
#define USART_StopBits_1_5 ((uint16_t)0x3000)
|
||||||
|
|
||||||
|
/* USART_Parity */
|
||||||
|
#define USART_Parity_No ((uint16_t)0x0000)
|
||||||
|
#define USART_Parity_Even ((uint16_t)0x0400)
|
||||||
|
#define USART_Parity_Odd ((uint16_t)0x0600)
|
||||||
|
|
||||||
|
/* USART_Mode */
|
||||||
|
#define USART_Mode_Rx ((uint16_t)0x0004)
|
||||||
|
#define USART_Mode_Tx ((uint16_t)0x0008)
|
||||||
|
|
||||||
|
/* USART_Hardware_Flow_Control */
|
||||||
|
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
|
||||||
|
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
|
||||||
|
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
|
||||||
|
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
|
||||||
|
|
||||||
|
/* USART_Clock */
|
||||||
|
#define USART_Clock_Disable ((uint16_t)0x0000)
|
||||||
|
#define USART_Clock_Enable ((uint16_t)0x0800)
|
||||||
|
|
||||||
|
/* USART_Clock_Polarity */
|
||||||
|
#define USART_CPOL_Low ((uint16_t)0x0000)
|
||||||
|
#define USART_CPOL_High ((uint16_t)0x0400)
|
||||||
|
|
||||||
|
/* USART_Clock_Phase */
|
||||||
|
#define USART_CPHA_1Edge ((uint16_t)0x0000)
|
||||||
|
#define USART_CPHA_2Edge ((uint16_t)0x0200)
|
||||||
|
|
||||||
|
/* USART_Last_Bit */
|
||||||
|
#define USART_LastBit_Disable ((uint16_t)0x0000)
|
||||||
|
#define USART_LastBit_Enable ((uint16_t)0x0100)
|
||||||
|
|
||||||
|
/* USART_Interrupt_definition */
|
||||||
|
#define USART_IT_PE ((uint16_t)0x0028)
|
||||||
|
#define USART_IT_TXE ((uint16_t)0x0727)
|
||||||
|
#define USART_IT_TC ((uint16_t)0x0626)
|
||||||
|
#define USART_IT_RXNE ((uint16_t)0x0525)
|
||||||
|
#define USART_IT_ORE_RX ((uint16_t)0x0325)
|
||||||
|
#define USART_IT_IDLE ((uint16_t)0x0424)
|
||||||
|
#define USART_IT_LBD ((uint16_t)0x0846)
|
||||||
|
#define USART_IT_CTS ((uint16_t)0x096A)
|
||||||
|
#define USART_IT_ERR ((uint16_t)0x0060)
|
||||||
|
#define USART_IT_ORE_ER ((uint16_t)0x0360)
|
||||||
|
#define USART_IT_NE ((uint16_t)0x0260)
|
||||||
|
#define USART_IT_FE ((uint16_t)0x0160)
|
||||||
|
|
||||||
|
#define USART_IT_ORE USART_IT_ORE_ER
|
||||||
|
|
||||||
|
/* USART_DMA_Requests */
|
||||||
|
#define USART_DMAReq_Tx ((uint16_t)0x0080)
|
||||||
|
#define USART_DMAReq_Rx ((uint16_t)0x0040)
|
||||||
|
|
||||||
|
/* USART_WakeUp_methods */
|
||||||
|
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
|
||||||
|
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
|
||||||
|
|
||||||
|
/* USART_LIN_Break_Detection_Length */
|
||||||
|
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
|
||||||
|
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
|
||||||
|
|
||||||
|
/* USART_IrDA_Low_Power */
|
||||||
|
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
|
||||||
|
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* USART_Flags */
|
||||||
|
#define USART_FLAG_CTS ((uint16_t)0x0200)
|
||||||
|
#define USART_FLAG_LBD ((uint16_t)0x0100)
|
||||||
|
#define USART_FLAG_TXE ((uint16_t)0x0080)
|
||||||
|
#define USART_FLAG_TC ((uint16_t)0x0040)
|
||||||
|
#define USART_FLAG_RXNE ((uint16_t)0x0020)
|
||||||
|
#define USART_FLAG_IDLE ((uint16_t)0x0010)
|
||||||
|
#define USART_FLAG_ORE ((uint16_t)0x0008)
|
||||||
|
#define USART_FLAG_NE ((uint16_t)0x0004)
|
||||||
|
#define USART_FLAG_FE ((uint16_t)0x0002)
|
||||||
|
#define USART_FLAG_PE ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
|
||||||
|
void USART_DeInit(USART_TypeDef* USARTx);
|
||||||
|
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||||
|
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||||
|
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||||
|
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||||
|
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
|
||||||
|
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
|
||||||
|
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||||
|
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
|
||||||
|
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
|
||||||
|
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||||
|
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||||
|
void USART_SendBreak(USART_TypeDef* USARTx);
|
||||||
|
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||||
|
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||||
|
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
|
||||||
|
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||||
|
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||||
|
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||||
|
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,834 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : system_ch32v30x.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/05/22
|
||||||
|
* Description : CH32V30x Device Peripheral Access Layer System Header File.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __CH32V30x_USB_H
|
||||||
|
#define __CH32V30x_USB_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************/
|
||||||
|
/* Header File */
|
||||||
|
#include "stdint.h"
|
||||||
|
|
||||||
|
/*******************************************************************************/
|
||||||
|
/* USB Communication Related Macro Definition */
|
||||||
|
/* USB Endpoint0 Size */
|
||||||
|
#ifndef DEFAULT_ENDP0_SIZE
|
||||||
|
#define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0
|
||||||
|
#endif
|
||||||
|
#ifndef MAX_PACKET_SIZE
|
||||||
|
#define MAX_PACKET_SIZE 64 // maximum packet size
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB PID */
|
||||||
|
#ifndef USB_PID_SETUP
|
||||||
|
#define USB_PID_NULL 0x00
|
||||||
|
#define USB_PID_SOF 0x05
|
||||||
|
#define USB_PID_SETUP 0x0D
|
||||||
|
#define USB_PID_IN 0x09
|
||||||
|
#define USB_PID_OUT 0x01
|
||||||
|
#define USB_PID_NYET 0x06
|
||||||
|
#define USB_PID_ACK 0x02
|
||||||
|
#define USB_PID_NAK 0x0A
|
||||||
|
#define USB_PID_STALL 0x0E
|
||||||
|
#define USB_PID_DATA0 0x03
|
||||||
|
#define USB_PID_DATA1 0x0B
|
||||||
|
#define USB_PID_DATA2 0x07
|
||||||
|
#define USB_PID_MDATA 0x0F
|
||||||
|
#define USB_PID_PRE 0x0C
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB standard device request code */
|
||||||
|
#ifndef USB_GET_DESCRIPTOR
|
||||||
|
#define USB_GET_STATUS 0x00
|
||||||
|
#define USB_CLEAR_FEATURE 0x01
|
||||||
|
#define USB_SET_FEATURE 0x03
|
||||||
|
#define USB_SET_ADDRESS 0x05
|
||||||
|
#define USB_GET_DESCRIPTOR 0x06
|
||||||
|
#define USB_SET_DESCRIPTOR 0x07
|
||||||
|
#define USB_GET_CONFIGURATION 0x08
|
||||||
|
#define USB_SET_CONFIGURATION 0x09
|
||||||
|
#define USB_GET_INTERFACE 0x0A
|
||||||
|
#define USB_SET_INTERFACE 0x0B
|
||||||
|
#define USB_SYNCH_FRAME 0x0C
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define DEF_STRING_DESC_LANG 0x00
|
||||||
|
#define DEF_STRING_DESC_MANU 0x01
|
||||||
|
#define DEF_STRING_DESC_PROD 0x02
|
||||||
|
#define DEF_STRING_DESC_SERN 0x03
|
||||||
|
|
||||||
|
/* USB hub class request code */
|
||||||
|
#ifndef HUB_GET_DESCRIPTOR
|
||||||
|
#define HUB_GET_STATUS 0x00
|
||||||
|
#define HUB_CLEAR_FEATURE 0x01
|
||||||
|
#define HUB_GET_STATE 0x02
|
||||||
|
#define HUB_SET_FEATURE 0x03
|
||||||
|
#define HUB_GET_DESCRIPTOR 0x06
|
||||||
|
#define HUB_SET_DESCRIPTOR 0x07
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB HID class request code */
|
||||||
|
#ifndef HID_GET_REPORT
|
||||||
|
#define HID_GET_REPORT 0x01
|
||||||
|
#define HID_GET_IDLE 0x02
|
||||||
|
#define HID_GET_PROTOCOL 0x03
|
||||||
|
#define HID_SET_REPORT 0x09
|
||||||
|
#define HID_SET_IDLE 0x0A
|
||||||
|
#define HID_SET_PROTOCOL 0x0B
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB CDC Class request code */
|
||||||
|
#ifndef CDC_GET_LINE_CODING
|
||||||
|
#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */
|
||||||
|
#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */
|
||||||
|
#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */
|
||||||
|
#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Bit Define for USB Request Type */
|
||||||
|
#ifndef USB_REQ_TYP_MASK
|
||||||
|
#define USB_REQ_TYP_IN 0x80
|
||||||
|
#define USB_REQ_TYP_OUT 0x00
|
||||||
|
#define USB_REQ_TYP_READ 0x80
|
||||||
|
#define USB_REQ_TYP_WRITE 0x00
|
||||||
|
#define USB_REQ_TYP_MASK 0x60
|
||||||
|
#define USB_REQ_TYP_STANDARD 0x00
|
||||||
|
#define USB_REQ_TYP_CLASS 0x20
|
||||||
|
#define USB_REQ_TYP_VENDOR 0x40
|
||||||
|
#define USB_REQ_TYP_RESERVED 0x60
|
||||||
|
#define USB_REQ_RECIP_MASK 0x1F
|
||||||
|
#define USB_REQ_RECIP_DEVICE 0x00
|
||||||
|
#define USB_REQ_RECIP_INTERF 0x01
|
||||||
|
#define USB_REQ_RECIP_ENDP 0x02
|
||||||
|
#define USB_REQ_RECIP_OTHER 0x03
|
||||||
|
#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01
|
||||||
|
#define USB_REQ_FEAT_ENDP_HALT 0x00
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB Descriptor Type */
|
||||||
|
#ifndef USB_DESCR_TYP_DEVICE
|
||||||
|
#define USB_DESCR_TYP_DEVICE 0x01
|
||||||
|
#define USB_DESCR_TYP_CONFIG 0x02
|
||||||
|
#define USB_DESCR_TYP_STRING 0x03
|
||||||
|
#define USB_DESCR_TYP_INTERF 0x04
|
||||||
|
#define USB_DESCR_TYP_ENDP 0x05
|
||||||
|
#define USB_DESCR_TYP_QUALIF 0x06
|
||||||
|
#define USB_DESCR_TYP_SPEED 0x07
|
||||||
|
#define USB_DESCR_TYP_OTG 0x09
|
||||||
|
#define USB_DESCR_TYP_BOS 0X0F
|
||||||
|
#define USB_DESCR_TYP_HID 0x21
|
||||||
|
#define USB_DESCR_TYP_REPORT 0x22
|
||||||
|
#define USB_DESCR_TYP_PHYSIC 0x23
|
||||||
|
#define USB_DESCR_TYP_CS_INTF 0x24
|
||||||
|
#define USB_DESCR_TYP_CS_ENDP 0x25
|
||||||
|
#define USB_DESCR_TYP_HUB 0x29
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB Device Class */
|
||||||
|
#ifndef USB_DEV_CLASS_HUB
|
||||||
|
#define USB_DEV_CLASS_RESERVED 0x00
|
||||||
|
#define USB_DEV_CLASS_AUDIO 0x01
|
||||||
|
#define USB_DEV_CLASS_COMMUNIC 0x02
|
||||||
|
#define USB_DEV_CLASS_HID 0x03
|
||||||
|
#define USB_DEV_CLASS_MONITOR 0x04
|
||||||
|
#define USB_DEV_CLASS_PHYSIC_IF 0x05
|
||||||
|
#define USB_DEV_CLASS_POWER 0x06
|
||||||
|
#define USB_DEV_CLASS_IMAGE 0x06
|
||||||
|
#define USB_DEV_CLASS_PRINTER 0x07
|
||||||
|
#define USB_DEV_CLASS_STORAGE 0x08
|
||||||
|
#define USB_DEV_CLASS_HUB 0x09
|
||||||
|
#define USB_DEV_CLASS_VEN_SPEC 0xFF
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB Hub Class Request */
|
||||||
|
#ifndef HUB_GET_HUB_DESCRIPTOR
|
||||||
|
#define HUB_CLEAR_HUB_FEATURE 0x20
|
||||||
|
#define HUB_CLEAR_PORT_FEATURE 0x23
|
||||||
|
#define HUB_GET_BUS_STATE 0xA3
|
||||||
|
#define HUB_GET_HUB_DESCRIPTOR 0xA0
|
||||||
|
#define HUB_GET_HUB_STATUS 0xA0
|
||||||
|
#define HUB_GET_PORT_STATUS 0xA3
|
||||||
|
#define HUB_SET_HUB_DESCRIPTOR 0x20
|
||||||
|
#define HUB_SET_HUB_FEATURE 0x20
|
||||||
|
#define HUB_SET_PORT_FEATURE 0x23
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Hub Class Feature Selectors */
|
||||||
|
#ifndef HUB_PORT_RESET
|
||||||
|
#define HUB_C_HUB_LOCAL_POWER 0
|
||||||
|
#define HUB_C_HUB_OVER_CURRENT 1
|
||||||
|
#define HUB_PORT_CONNECTION 0
|
||||||
|
#define HUB_PORT_ENABLE 1
|
||||||
|
#define HUB_PORT_SUSPEND 2
|
||||||
|
#define HUB_PORT_OVER_CURRENT 3
|
||||||
|
#define HUB_PORT_RESET 4
|
||||||
|
#define HUB_PORT_POWER 8
|
||||||
|
#define HUB_PORT_LOW_SPEED 9
|
||||||
|
#define HUB_C_PORT_CONNECTION 16
|
||||||
|
#define HUB_C_PORT_ENABLE 17
|
||||||
|
#define HUB_C_PORT_SUSPEND 18
|
||||||
|
#define HUB_C_PORT_OVER_CURRENT 19
|
||||||
|
#define HUB_C_PORT_RESET 20
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB UDisk */
|
||||||
|
#ifndef USB_BO_CBW_SIZE
|
||||||
|
#define USB_BO_CBW_SIZE 0x1F
|
||||||
|
#define USB_BO_CSW_SIZE 0x0D
|
||||||
|
#endif
|
||||||
|
#ifndef USB_BO_CBW_SIG0
|
||||||
|
#define USB_BO_CBW_SIG0 0x55
|
||||||
|
#define USB_BO_CBW_SIG1 0x53
|
||||||
|
#define USB_BO_CBW_SIG2 0x42
|
||||||
|
#define USB_BO_CBW_SIG3 0x43
|
||||||
|
#define USB_BO_CSW_SIG0 0x55
|
||||||
|
#define USB_BO_CSW_SIG1 0x53
|
||||||
|
#define USB_BO_CSW_SIG2 0x42
|
||||||
|
#define USB_BO_CSW_SIG3 0x53
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* USBHS Clock Configuration Related Macro Definition */
|
||||||
|
#define USB_CLK_SRC 0x80000000
|
||||||
|
#define USBHS_PLL_ALIVE 0x40000000
|
||||||
|
#define USBHS_PLL_CKREF_MASK 0x30000000
|
||||||
|
#define USBHS_PLL_CKREF_3M 0x00000000
|
||||||
|
#define USBHS_PLL_CKREF_4M 0x10000000
|
||||||
|
#define USBHS_PLL_CKREF_8M 0x20000000
|
||||||
|
#define USBHS_PLL_CKREF_5M 0x30000000
|
||||||
|
#define USBHS_PLL_SRC 0x08000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_MASK 0x07000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV1 0x00000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV2 0x01000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV3 0x02000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV4 0x03000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV5 0x04000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV6 0x05000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV7 0x06000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV8 0x07000000
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************/
|
||||||
|
/* USBHS Related Register Macro Definition */
|
||||||
|
|
||||||
|
/* R8_USB_CTRL */
|
||||||
|
#define USBHS_UC_HOST_MODE 0x80
|
||||||
|
#define USBHS_UC_SPEED_TYPE 0x60
|
||||||
|
#define USBHS_UC_SPEED_LOW 0x40
|
||||||
|
#define USBHS_UC_SPEED_FULL 0x00
|
||||||
|
#define USBHS_UC_SPEED_HIGH 0x20
|
||||||
|
#define USBHS_UC_DEV_PU_EN 0x10
|
||||||
|
#define USBHS_UC_INT_BUSY 0x08
|
||||||
|
#define USBHS_UC_RESET_SIE 0x04
|
||||||
|
#define USBHS_UC_CLR_ALL 0x02
|
||||||
|
#define USBHS_UC_DMA_EN 0x01
|
||||||
|
|
||||||
|
/* R8_USB_INT_EN */
|
||||||
|
#define USBHS_UIE_DEV_NAK 0x80
|
||||||
|
#define USBHS_UIE_ISO_ACT 0x40
|
||||||
|
#define USBHS_UIE_SETUP_ACT 0x20
|
||||||
|
#define USBHS_UIE_FIFO_OV 0x10
|
||||||
|
#define USBHS_UIE_SOF_ACT 0x08
|
||||||
|
#define USBHS_UIE_SUSPEND 0x04
|
||||||
|
#define USBHS_UIE_TRANSFER 0x02
|
||||||
|
#define USBHS_UIE_DETECT 0x01
|
||||||
|
#define USBHS_UIE_BUS_RST 0x01
|
||||||
|
|
||||||
|
/* R16_USB_DEV_AD */
|
||||||
|
#define USBHS_MASK_USB_ADDR 0x7F
|
||||||
|
|
||||||
|
/* R16_USB_FRAME_NO */
|
||||||
|
#define USBHS_MICRO_FRAME_NUM 0xE000
|
||||||
|
#define USBHS_SOF_FRAME_NUM 0x07FF
|
||||||
|
|
||||||
|
/* R8_USB_SUSPEND */
|
||||||
|
#define USBHS_USB_LINESTATE 0x30
|
||||||
|
#define USBHS_USB_WAKEUP_ST 0x04
|
||||||
|
#define USBHS_USB_SYS_MOD 0x03
|
||||||
|
|
||||||
|
/* R8_USB_SPEED_TYPE */
|
||||||
|
#define USBHS_USB_SPEED_TYPE 0x03
|
||||||
|
#define USBHS_USB_SPEED_LOW 0x02
|
||||||
|
#define USBHS_USB_SPEED_FULL 0x00
|
||||||
|
#define USBHS_USB_SPEED_HIGH 0x01
|
||||||
|
|
||||||
|
/* R8_USB_MIS_ST */
|
||||||
|
#define USBHS_UMS_SOF_PRES 0x80
|
||||||
|
#define USBHS_UMS_SOF_ACT 0x40
|
||||||
|
#define USBHS_UMS_SIE_FREE 0x20
|
||||||
|
#define USBHS_UMS_R_FIFO_RDY 0x10
|
||||||
|
#define USBHS_UMS_BUS_RESET 0x08
|
||||||
|
#define USBHS_UMS_SUSPEND 0x04
|
||||||
|
#define USBHS_UMS_DEV_ATTACH 0x02
|
||||||
|
#define USBHS_UMS_SPLIT_CAN 0x01
|
||||||
|
|
||||||
|
/* R8_USB_INT_FG */
|
||||||
|
#define USBHS_UIF_ISO_ACT 0x40
|
||||||
|
#define USBHS_UIF_SETUP_ACT 0x20
|
||||||
|
#define USBHS_UIF_FIFO_OV 0x10
|
||||||
|
#define USBHS_UIF_HST_SOF 0x08
|
||||||
|
#define USBHS_UIF_SUSPEND 0x04
|
||||||
|
#define USBHS_UIF_TRANSFER 0x02
|
||||||
|
#define USBHS_UIF_DETECT 0x01
|
||||||
|
#define USBHS_UIF_BUS_RST 0x01
|
||||||
|
|
||||||
|
/* R8_USB_INT_ST */
|
||||||
|
#define USBHS_UIS_IS_NAK 0x80
|
||||||
|
#define USBHS_UIS_TOG_OK 0x40
|
||||||
|
#define USBHS_UIS_TOKEN_MASK 0x30
|
||||||
|
#define USBHS_UIS_TOKEN_OUT 0x00
|
||||||
|
#define USBHS_UIS_TOKEN_SOF 0x10
|
||||||
|
#define USBHS_UIS_TOKEN_IN 0x20
|
||||||
|
#define USBHS_UIS_TOKEN_SETUP 0x30
|
||||||
|
#define USBHS_UIS_ENDP_MASK 0x0F
|
||||||
|
#define USBHS_UIS_H_RES_MASK 0x0F
|
||||||
|
|
||||||
|
/* R16_USB_RX_LEN */
|
||||||
|
#define USBHS_USB_RX_LEN 0xFFFF
|
||||||
|
|
||||||
|
/* R32_UEP_CONFIG */
|
||||||
|
#define USBHS_UEP15_R_EN 0x80000000
|
||||||
|
#define USBHS_UEP14_R_EN 0x40000000
|
||||||
|
#define USBHS_UEP13_R_EN 0x20000000
|
||||||
|
#define USBHS_UEP12_R_EN 0x10000000
|
||||||
|
#define USBHS_UEP11_R_EN 0x08000000
|
||||||
|
#define USBHS_UEP10_R_EN 0x04000000
|
||||||
|
#define USBHS_UEP9_R_EN 0x02000000
|
||||||
|
#define USBHS_UEP8_R_EN 0x01000000
|
||||||
|
#define USBHS_UEP7_R_EN 0x00800000
|
||||||
|
#define USBHS_UEP6_R_EN 0x00400000
|
||||||
|
#define USBHS_UEP5_R_EN 0x00200000
|
||||||
|
#define USBHS_UEP4_R_EN 0x00100000
|
||||||
|
#define USBHS_UEP3_R_EN 0x00080000
|
||||||
|
#define USBHS_UEP2_R_EN 0x00040000
|
||||||
|
#define USBHS_UEP1_R_EN 0x00020000
|
||||||
|
#define USBHS_UEP0_R_EN 0x00010000
|
||||||
|
#define USBHS_UEP15_T_EN 0x00008000
|
||||||
|
#define USBHS_UEP14_T_EN 0x00004000
|
||||||
|
#define USBHS_UEP13_T_EN 0x00002000
|
||||||
|
#define USBHS_UEP12_T_EN 0x00001000
|
||||||
|
#define USBHS_UEP11_T_EN 0x00000800
|
||||||
|
#define USBHS_UEP10_T_EN 0x00000400
|
||||||
|
#define USBHS_UEP9_T_EN 0x00000200
|
||||||
|
#define USBHS_UEP8_T_EN 0x00000100
|
||||||
|
#define USBHS_UEP7_T_EN 0x00000080
|
||||||
|
#define USBHS_UEP6_T_EN 0x00000040
|
||||||
|
#define USBHS_UEP5_T_EN 0x00000020
|
||||||
|
#define USBHS_UEP4_T_EN 0x00000010
|
||||||
|
#define USBHS_UEP3_T_EN 0x00000008
|
||||||
|
#define USBHS_UEP2_T_EN 0x00000004
|
||||||
|
#define USBHS_UEP1_T_EN 0x00000002
|
||||||
|
#define USBHS_UEP0_T_EN 0x00000001
|
||||||
|
|
||||||
|
/* R32_UEP_TYPE */
|
||||||
|
#define USBHS_UEP15_R_TYPE 0x80000000
|
||||||
|
#define USBHS_UEP14_R_TYPE 0x40000000
|
||||||
|
#define USBHS_UEP13_R_TYPE 0x20000000
|
||||||
|
#define USBHS_UEP12_R_TYPE 0x10000000
|
||||||
|
#define USBHS_UEP11_R_TYPE 0x08000000
|
||||||
|
#define USBHS_UEP10_R_TYPE 0x04000000
|
||||||
|
#define USBHS_UEP9_R_TYPE 0x02000000
|
||||||
|
#define USBHS_UEP8_R_TYPE 0x01000000
|
||||||
|
#define USBHS_UEP7_R_TYPE 0x00800000
|
||||||
|
#define USBHS_UEP6_R_TYPE 0x00400000
|
||||||
|
#define USBHS_UEP5_R_TYPE 0x00200000
|
||||||
|
#define USBHS_UEP4_R_TYPE 0x00100000
|
||||||
|
#define USBHS_UEP3_R_TYPE 0x00080000
|
||||||
|
#define USBHS_UEP2_R_TYPE 0x00040000
|
||||||
|
#define USBHS_UEP1_R_TYPE 0x00020000
|
||||||
|
#define USBHS_UEP0_R_TYPE 0x00010000
|
||||||
|
#define USBHS_UEP15_T_TYPE 0x00008000
|
||||||
|
#define USBHS_UEP14_T_TYPE 0x00004000
|
||||||
|
#define USBHS_UEP13_T_TYPE 0x00002000
|
||||||
|
#define USBHS_UEP12_T_TYPE 0x00001000
|
||||||
|
#define USBHS_UEP11_T_TYPE 0x00000800
|
||||||
|
#define USBHS_UEP10_T_TYPE 0x00000400
|
||||||
|
#define USBHS_UEP9_T_TYPE 0x00000200
|
||||||
|
#define USBHS_UEP8_T_TYPE 0x00000100
|
||||||
|
#define USBHS_UEP7_T_TYPE 0x00000080
|
||||||
|
#define USBHS_UEP6_T_TYPE 0x00000040
|
||||||
|
#define USBHS_UEP5_T_TYPE 0x00000020
|
||||||
|
#define USBHS_UEP4_T_TYPE 0x00000010
|
||||||
|
#define USBHS_UEP3_T_TYPE 0x00000008
|
||||||
|
#define USBHS_UEP2_T_TYPE 0x00000004
|
||||||
|
#define USBHS_UEP1_T_TYPE 0x00000002
|
||||||
|
#define USBHS_UEP0_T_TYPE 0x00000001
|
||||||
|
|
||||||
|
/* R32_UEP_BUF_MOD */
|
||||||
|
#define USBHS_UEP15_ISO_BUF_MOD 0x80000000
|
||||||
|
#define USBHS_UEP14_ISO_BUF_MOD 0x40000000
|
||||||
|
#define USBHS_UEP13_ISO_BUF_MOD 0x20000000
|
||||||
|
#define USBHS_UEP12_ISO_BUF_MOD 0x10000000
|
||||||
|
#define USBHS_UEP11_ISO_BUF_MOD 0x08000000
|
||||||
|
#define USBHS_UEP10_ISO_BUF_MOD 0x04000000
|
||||||
|
#define USBHS_UEP9_ISO_BUF_MOD 0x02000000
|
||||||
|
#define USBHS_UEP8_ISO_BUF_MOD 0x01000000
|
||||||
|
#define USBHS_UEP7_ISO_BUF_MOD 0x00800000
|
||||||
|
#define USBHS_UEP6_ISO_BUF_MOD 0x00400000
|
||||||
|
#define USBHS_UEP5_ISO_BUF_MOD 0x00200000
|
||||||
|
#define USBHS_UEP4_ISO_BUF_MOD 0x00100000
|
||||||
|
#define USBHS_UEP3_ISO_BUF_MOD 0x00080000
|
||||||
|
#define USBHS_UEP2_ISO_BUF_MOD 0x00040000
|
||||||
|
#define USBHS_UEP1_ISO_BUF_MOD 0x00020000
|
||||||
|
#define USBHS_UEP0_ISO_BUF_MOD 0x00010000
|
||||||
|
#define USBHS_UEP15_BUF_MOD 0x00008000
|
||||||
|
#define USBHS_UEP14_BUF_MOD 0x00004000
|
||||||
|
#define USBHS_UEP13_BUF_MOD 0x00002000
|
||||||
|
#define USBHS_UEP12_BUF_MOD 0x00001000
|
||||||
|
#define USBHS_UEP11_BUF_MOD 0x00000800
|
||||||
|
#define USBHS_UEP10_BUF_MOD 0x00000400
|
||||||
|
#define USBHS_UEP9_BUF_MOD 0x00000200
|
||||||
|
#define USBHS_UEP8_BUF_MOD 0x00000100
|
||||||
|
#define USBHS_UEP7_BUF_MOD 0x00000080
|
||||||
|
#define USBHS_UEP6_BUF_MOD 0x00000040
|
||||||
|
#define USBHS_UEP5_BUF_MOD 0x00000020
|
||||||
|
#define USBHS_UEP4_BUF_MOD 0x00000010
|
||||||
|
#define USBHS_UEP3_BUF_MOD 0x00000008
|
||||||
|
#define USBHS_UEP2_BUF_MOD 0x00000004
|
||||||
|
#define USBHS_UEP1_BUF_MOD 0x00000002
|
||||||
|
#define USBHS_UEP0_BUF_MOD 0x00000001
|
||||||
|
|
||||||
|
/* R32_UEP0_DMA */
|
||||||
|
#define USBHS_UEP0_DMA 0x0000FFFF
|
||||||
|
|
||||||
|
/* R32_UEPn_TX_DMA, n=1-15 */
|
||||||
|
#define USBHS_UEPn_TX_DMA 0x0000FFFF
|
||||||
|
|
||||||
|
/* R32_UEPn_RX_DMA, n=1-15 */
|
||||||
|
#define USBHS_UEPn_RX_DMA 0x0000FFFF
|
||||||
|
|
||||||
|
/* R16_UEPn_MAX_LEN, n=0-15 */
|
||||||
|
#define USBHS_UEPn_MAX_LEN 0x07FF
|
||||||
|
|
||||||
|
/* R16_UEPn_T_LEN, n=0-15 */
|
||||||
|
#define USBHS_UEPn_T_LEN 0x07FF
|
||||||
|
|
||||||
|
/* R8_UEPn_TX_CTRL, n=0-15 */
|
||||||
|
#define USBHS_UEP_T_TOG_AUTO 0x20
|
||||||
|
#define USBHS_UEP_T_TOG_MASK 0x18
|
||||||
|
#define USBHS_UEP_T_TOG_DATA0 0x00
|
||||||
|
#define USBHS_UEP_T_TOG_DATA1 0x08
|
||||||
|
#define USBHS_UEP_T_TOG_DATA2 0x10
|
||||||
|
#define USBHS_UEP_T_TOG_MDATA 0x18
|
||||||
|
#define USBHS_UEP_T_RES_MASK 0x03
|
||||||
|
#define USBHS_UEP_T_RES_ACK 0x00
|
||||||
|
#define USBHS_UEP_T_RES_NYET 0x01
|
||||||
|
#define USBHS_UEP_T_RES_NAK 0x02
|
||||||
|
#define USBHS_UEP_T_RES_STALL 0x03
|
||||||
|
|
||||||
|
/* R8_UEPn_TX_CTRL, n=0-15 */
|
||||||
|
#define USBHS_UEP_R_TOG_AUTO 0x20
|
||||||
|
#define USBHS_UEP_R_TOG_MASK 0x18
|
||||||
|
#define USBHS_UEP_R_TOG_DATA0 0x00
|
||||||
|
#define USBHS_UEP_R_TOG_DATA1 0x08
|
||||||
|
#define USBHS_UEP_R_TOG_DATA2 0x10
|
||||||
|
#define USBHS_UEP_R_TOG_MDATA 0x18
|
||||||
|
#define USBHS_UEP_R_RES_MASK 0x03
|
||||||
|
#define USBHS_UEP_R_RES_ACK 0x00
|
||||||
|
#define USBHS_UEP_R_RES_NYET 0x01
|
||||||
|
#define USBHS_UEP_R_RES_NAK 0x02
|
||||||
|
#define USBHS_UEP_R_RES_STALL 0x03
|
||||||
|
|
||||||
|
/* R8_UHOST_CTRL */
|
||||||
|
#define USBHS_UH_SOF_EN 0x80
|
||||||
|
#define USBHS_UH_SOF_FREE 0x40
|
||||||
|
#define USBHS_UH_PHY_SUSPENDM 0x10
|
||||||
|
#define USBHS_UH_REMOTE_WKUP 0x08
|
||||||
|
#define USBHS_UH_TX_BUS_RESUME 0x04
|
||||||
|
#define USBHS_UH_TX_BUS_SUSPEND 0x02
|
||||||
|
#define USBHS_UH_TX_BUS_RESET 0x01
|
||||||
|
|
||||||
|
/* R32_UH_CONFIG */
|
||||||
|
#define USBHS_UH_EP_RX_EN 0x00040000
|
||||||
|
#define USBHS_UH_EP_TX_EN 0x00000008
|
||||||
|
|
||||||
|
/* R32_UH_EP_TYPE */
|
||||||
|
#define USBHS_UH_EP_RX_TYPE 0x00040000
|
||||||
|
#define USBHS_UH_EP_TX_TYPE 0x00000008
|
||||||
|
|
||||||
|
/* R32_UH_RX_DMA */
|
||||||
|
#define USBHS_UH_RX_DMA 0x0000FFFC
|
||||||
|
|
||||||
|
/* R32_UH_TX_DMA */
|
||||||
|
#define USBHS_UH_TX_DMA 0x0000FFFF
|
||||||
|
|
||||||
|
/* R16_UH_RX_MAX_LEN */
|
||||||
|
#define USBHS_UH_RX_MAX_LEN 0x07FF
|
||||||
|
|
||||||
|
/* R8_UH_EP_PID */
|
||||||
|
#define USBHS_UH_TOKEN_MASK 0xF0
|
||||||
|
#define USBHS_UH_ENDP_MASK 0x0F
|
||||||
|
|
||||||
|
/* R8_UH_RX_CTRL */
|
||||||
|
#define USBHS_UH_R_DATA_NO 0x40
|
||||||
|
#define USBHS_UH_R_TOG_AUTO 0x20
|
||||||
|
#define USBHS_UH_R_TOG_MASK 0x18
|
||||||
|
#define USBHS_UH_R_TOG_DATA0 0x00
|
||||||
|
#define USBHS_UH_R_TOG_DATA1 0x08
|
||||||
|
#define USBHS_UH_R_TOG_DATA2 0x10
|
||||||
|
#define USBHS_UH_R_TOG_MDATA 0x18
|
||||||
|
#define USBHS_UH_R_RES_NO 0x04
|
||||||
|
#define USBHS_UH_R_RES_MASK 0x03
|
||||||
|
#define USBHS_UH_R_RES_ACK 0x00
|
||||||
|
#define USBHS_UH_R_RES_NYET 0x01
|
||||||
|
#define USBHS_UH_R_RES_NAK 0x02
|
||||||
|
#define USBHS_UH_R_RES_STALL 0x03
|
||||||
|
|
||||||
|
/* R16_UH_TX_LEN */
|
||||||
|
#define USBHS_UH_TX_LEN 0x07FF
|
||||||
|
|
||||||
|
/* R8_UH_TX_CTRL */
|
||||||
|
#define USBHS_UH_T_DATA_NO 0x40
|
||||||
|
#define USBHS_UH_T_AUTO_TOG 0x20
|
||||||
|
#define USBHS_UH_T_TOG_MASK 0x18
|
||||||
|
#define USBHS_UH_T_TOG_DATA0 0x00
|
||||||
|
#define USBHS_UH_T_TOG_DATA1 0x08
|
||||||
|
#define USBHS_UH_T_TOG_DATA2 0x10
|
||||||
|
#define USBHS_UH_T_TOG_MDATA 0x18
|
||||||
|
#define USBHS_UH_T_RES_NO 0x04
|
||||||
|
#define USBHS_UH_T_RES_MASK 0x03
|
||||||
|
#define USBHS_UH_T_RES_ACK 0x00
|
||||||
|
#define USBHS_UH_T_RES_NYET 0x01
|
||||||
|
#define USBHS_UH_T_RES_NAK 0x02
|
||||||
|
#define USBHS_UH_T_RES_STALL 0x03
|
||||||
|
|
||||||
|
/* R16_UH_SPLIT_DATA */
|
||||||
|
#define USBHS_UH_SPLIT_DATA 0x0FFF
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************/
|
||||||
|
/* USBFS Related Register Macro Definition */
|
||||||
|
|
||||||
|
/* R8_USB_CTRL */
|
||||||
|
#define USBFS_UC_HOST_MODE 0x80
|
||||||
|
#define USBFS_UC_LOW_SPEED 0x40
|
||||||
|
#define USBFS_UC_DEV_PU_EN 0x20
|
||||||
|
#define USBFS_UC_SYS_CTRL_MASK 0x30
|
||||||
|
#define USBFS_UC_SYS_CTRL0 0x00
|
||||||
|
#define USBFS_UC_SYS_CTRL1 0x10
|
||||||
|
#define USBFS_UC_SYS_CTRL2 0x20
|
||||||
|
#define USBFS_UC_SYS_CTRL3 0x30
|
||||||
|
#define USBFS_UC_INT_BUSY 0x08
|
||||||
|
#define USBFS_UC_RESET_SIE 0x04
|
||||||
|
#define USBFS_UC_CLR_ALL 0x02
|
||||||
|
#define USBFS_UC_DMA_EN 0x01
|
||||||
|
|
||||||
|
/* R8_USB_INT_EN */
|
||||||
|
#define USBFS_UIE_DEV_SOF 0x80
|
||||||
|
#define USBFS_UIE_DEV_NAK 0x40
|
||||||
|
#define USBFS_1WIRE_MODE 0x20
|
||||||
|
#define USBFS_UIE_FIFO_OV 0x10
|
||||||
|
#define USBFS_UIE_HST_SOF 0x08
|
||||||
|
#define USBFS_UIE_SUSPEND 0x04
|
||||||
|
#define USBFS_UIE_TRANSFER 0x02
|
||||||
|
#define USBFS_UIE_DETECT 0x01
|
||||||
|
#define USBFS_UIE_BUS_RST 0x01
|
||||||
|
|
||||||
|
/* R8_USB_DEV_AD */
|
||||||
|
#define USBFS_UDA_GP_BIT 0x80
|
||||||
|
#define USBFS_USB_ADDR_MASK 0x7F
|
||||||
|
|
||||||
|
/* R8_USB_MIS_ST */
|
||||||
|
#define USBFS_UMS_SOF_PRES 0x80
|
||||||
|
#define USBFS_UMS_SOF_ACT 0x40
|
||||||
|
#define USBFS_UMS_SIE_FREE 0x20
|
||||||
|
#define USBFS_UMS_R_FIFO_RDY 0x10
|
||||||
|
#define USBFS_UMS_BUS_RESET 0x08
|
||||||
|
#define USBFS_UMS_SUSPEND 0x04
|
||||||
|
#define USBFS_UMS_DM_LEVEL 0x02
|
||||||
|
#define USBFS_UMS_DEV_ATTACH 0x01
|
||||||
|
|
||||||
|
/* R8_USB_INT_FG */
|
||||||
|
#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received
|
||||||
|
#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
|
||||||
|
#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status
|
||||||
|
#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
|
||||||
|
#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
|
||||||
|
#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
|
||||||
|
#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
|
||||||
|
#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
|
||||||
|
#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
|
||||||
|
|
||||||
|
/* R8_USB_INT_ST */
|
||||||
|
#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode
|
||||||
|
#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
|
||||||
|
#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode
|
||||||
|
#define USBFS_UIS_TOKEN_OUT 0x00
|
||||||
|
#define USBFS_UIS_TOKEN_SOF 0x10
|
||||||
|
#define USBFS_UIS_TOKEN_IN 0x20
|
||||||
|
#define USBFS_UIS_TOKEN_SETUP 0x30
|
||||||
|
// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
|
||||||
|
// 00: OUT token PID received
|
||||||
|
// 01: SOF token PID received
|
||||||
|
// 10: IN token PID received
|
||||||
|
// 11: SETUP token PID received
|
||||||
|
#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode
|
||||||
|
#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
|
||||||
|
|
||||||
|
/* R32_USB_OTG_CR */
|
||||||
|
#define USBFS_CR_SESS_VTH 0x20
|
||||||
|
#define USBFS_CR_VBUS_VTH 0x10
|
||||||
|
#define USBFS_CR_OTG_EN 0x08
|
||||||
|
#define USBFS_CR_IDPU 0x04
|
||||||
|
#define USBFS_CR_CHARGE_VBUS 0x02
|
||||||
|
#define USBFS_CR_DISCHAR_VBUS 0x01
|
||||||
|
|
||||||
|
/* R32_USB_OTG_SR */
|
||||||
|
#define USBFS_SR_ID_DIG 0x08
|
||||||
|
#define USBFS_SR_SESS_END 0x04
|
||||||
|
#define USBFS_SR_SESS_VLD 0x02
|
||||||
|
#define USBFS_SR_VBUS_VLD 0x01
|
||||||
|
|
||||||
|
/* R8_UDEV_CTRL */
|
||||||
|
#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
|
||||||
|
#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
|
||||||
|
#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
|
||||||
|
#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
|
||||||
|
#define USBFS_UD_GP_BIT 0x02 // general purpose bit
|
||||||
|
#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable
|
||||||
|
|
||||||
|
/* R8_UEP4_1_MOD */
|
||||||
|
#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
|
||||||
|
#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
|
||||||
|
#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
|
||||||
|
#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
|
||||||
|
#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
|
||||||
|
#define USBFS_UEP4_BUF_MOD 0x01
|
||||||
|
|
||||||
|
/* R8_UEP2_3_MOD */
|
||||||
|
#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
|
||||||
|
#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
|
||||||
|
#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
|
||||||
|
#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
|
||||||
|
#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
|
||||||
|
#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
|
||||||
|
|
||||||
|
/* R8_UEP5_6_MOD */
|
||||||
|
#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT)
|
||||||
|
#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN)
|
||||||
|
#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6
|
||||||
|
#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT)
|
||||||
|
#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN)
|
||||||
|
#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5
|
||||||
|
|
||||||
|
/* R8_UEP7_MOD */
|
||||||
|
#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT)
|
||||||
|
#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN)
|
||||||
|
#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7
|
||||||
|
|
||||||
|
/* R8_UEPn_TX_CTRL */
|
||||||
|
#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
|
||||||
|
#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
|
||||||
|
#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN)
|
||||||
|
#define USBFS_UEP_T_RES_ACK 0x00
|
||||||
|
#define USBFS_UEP_T_RES_NONE 0x01
|
||||||
|
#define USBFS_UEP_T_RES_NAK 0x02
|
||||||
|
#define USBFS_UEP_T_RES_STALL 0x03
|
||||||
|
// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
|
||||||
|
// 00: DATA0 or DATA1 then expecting ACK (ready)
|
||||||
|
// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
|
||||||
|
// 10: NAK (busy)
|
||||||
|
// 11: STALL (error)
|
||||||
|
// host aux setup
|
||||||
|
|
||||||
|
/* R8_UEPn_RX_CTRL, n=0-7 */
|
||||||
|
#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
|
||||||
|
#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
|
||||||
|
#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT)
|
||||||
|
#define USBFS_UEP_R_RES_ACK 0x00
|
||||||
|
#define USBFS_UEP_R_RES_NONE 0x01
|
||||||
|
#define USBFS_UEP_R_RES_NAK 0x02
|
||||||
|
#define USBFS_UEP_R_RES_STALL 0x03
|
||||||
|
// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
|
||||||
|
// 00: ACK (ready)
|
||||||
|
// 01: no response, time out to host, for non-zero endpoint isochronous transactions
|
||||||
|
// 10: NAK (busy)
|
||||||
|
// 11: STALL (error)
|
||||||
|
|
||||||
|
/* R8_UHOST_CTRL */
|
||||||
|
#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
|
||||||
|
#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
|
||||||
|
#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
|
||||||
|
#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed
|
||||||
|
#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
|
||||||
|
#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
|
||||||
|
|
||||||
|
/* R32_UH_EP_MOD */
|
||||||
|
#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
|
||||||
|
#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
|
||||||
|
// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
|
||||||
|
// 0 x: disable endpoint and disable buffer
|
||||||
|
// 1 0: 64 bytes buffer for transmittal (OUT endpoint)
|
||||||
|
// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
|
||||||
|
#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
|
||||||
|
#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
|
||||||
|
// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
|
||||||
|
// 0 x: disable endpoint and disable buffer
|
||||||
|
// 1 0: 64 bytes buffer for receiving (IN endpoint)
|
||||||
|
// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
|
||||||
|
|
||||||
|
/* R16_UH_SETUP */
|
||||||
|
#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub
|
||||||
|
#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable
|
||||||
|
|
||||||
|
/* R8_UH_EP_PID */
|
||||||
|
#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer
|
||||||
|
#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer
|
||||||
|
|
||||||
|
/* R8_UH_RX_CTRL */
|
||||||
|
#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
||||||
|
#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
|
||||||
|
#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
|
||||||
|
|
||||||
|
/* R8_UH_TX_CTRL */
|
||||||
|
#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
||||||
|
#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
|
||||||
|
#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************/
|
||||||
|
/* Struct Definition */
|
||||||
|
|
||||||
|
/* USB Setup Request */
|
||||||
|
typedef struct __attribute__((packed)) _USB_SETUP_REQ
|
||||||
|
{
|
||||||
|
uint8_t bRequestType;
|
||||||
|
uint8_t bRequest;
|
||||||
|
uint16_t wValue;
|
||||||
|
uint16_t wIndex;
|
||||||
|
uint16_t wLength;
|
||||||
|
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
|
||||||
|
|
||||||
|
/* USB Device Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint16_t bcdUSB;
|
||||||
|
uint8_t bDeviceClass;
|
||||||
|
uint8_t bDeviceSubClass;
|
||||||
|
uint8_t bDeviceProtocol;
|
||||||
|
uint8_t bMaxPacketSize0;
|
||||||
|
uint16_t idVendor;
|
||||||
|
uint16_t idProduct;
|
||||||
|
uint16_t bcdDevice;
|
||||||
|
uint8_t iManufacturer;
|
||||||
|
uint8_t iProduct;
|
||||||
|
uint8_t iSerialNumber;
|
||||||
|
uint8_t bNumConfigurations;
|
||||||
|
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
|
||||||
|
|
||||||
|
/* USB Configuration Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint16_t wTotalLength;
|
||||||
|
uint8_t bNumInterfaces;
|
||||||
|
uint8_t bConfigurationValue;
|
||||||
|
uint8_t iConfiguration;
|
||||||
|
uint8_t bmAttributes;
|
||||||
|
uint8_t MaxPower;
|
||||||
|
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
|
||||||
|
|
||||||
|
/* USB Interface Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_INTERF_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint8_t bInterfaceNumber;
|
||||||
|
uint8_t bAlternateSetting;
|
||||||
|
uint8_t bNumEndpoints;
|
||||||
|
uint8_t bInterfaceClass;
|
||||||
|
uint8_t bInterfaceSubClass;
|
||||||
|
uint8_t bInterfaceProtocol;
|
||||||
|
uint8_t iInterface;
|
||||||
|
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
|
||||||
|
|
||||||
|
/* USB Endpoint Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint8_t bEndpointAddress;
|
||||||
|
uint8_t bmAttributes;
|
||||||
|
uint8_t wMaxPacketSizeL;
|
||||||
|
uint8_t wMaxPacketSizeH;
|
||||||
|
uint8_t bInterval;
|
||||||
|
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
|
||||||
|
|
||||||
|
/* USB Configuration Descriptor Set */
|
||||||
|
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
|
||||||
|
{
|
||||||
|
USB_CFG_DESCR cfg_descr;
|
||||||
|
USB_ITF_DESCR itf_descr;
|
||||||
|
USB_ENDP_DESCR endp_descr[ 1 ];
|
||||||
|
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
|
||||||
|
|
||||||
|
/* USB HUB Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_HUB_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bDescLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint8_t bNbrPorts;
|
||||||
|
uint8_t wHubCharacteristicsL;
|
||||||
|
uint8_t wHubCharacteristicsH;
|
||||||
|
uint8_t bPwrOn2PwrGood;
|
||||||
|
uint8_t bHubContrCurrent;
|
||||||
|
uint8_t DeviceRemovable;
|
||||||
|
uint8_t PortPwrCtrlMask;
|
||||||
|
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
|
||||||
|
|
||||||
|
/* USB HID Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_HID_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint16_t bcdHID;
|
||||||
|
uint8_t bCountryCode;
|
||||||
|
uint8_t bNumDescriptors;
|
||||||
|
uint8_t bDescriptorTypeX;
|
||||||
|
uint8_t wDescriptorLengthL;
|
||||||
|
uint8_t wDescriptorLengthH;
|
||||||
|
} USB_HID_DESCR, *PUSB_HID_DESCR;
|
||||||
|
|
||||||
|
/* USB UDisk */
|
||||||
|
typedef struct __attribute__((packed)) _UDISK_BOC_CBW
|
||||||
|
{
|
||||||
|
uint32_t mCBW_Sig;
|
||||||
|
uint32_t mCBW_Tag;
|
||||||
|
uint32_t mCBW_DataLen;
|
||||||
|
uint8_t mCBW_Flag;
|
||||||
|
uint8_t mCBW_LUN;
|
||||||
|
uint8_t mCBW_CB_Len;
|
||||||
|
uint8_t mCBW_CB_Buf[ 16 ];
|
||||||
|
} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
|
||||||
|
|
||||||
|
/* USB UDisk */
|
||||||
|
typedef struct __attribute__((packed)) _UDISK_BOC_CSW
|
||||||
|
{
|
||||||
|
uint32_t mCBW_Sig;
|
||||||
|
uint32_t mCBW_Tag;
|
||||||
|
uint32_t mCSW_Residue;
|
||||||
|
uint8_t mCSW_Status;
|
||||||
|
} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CH32V30x_USB_H */
|
||||||
@@ -0,0 +1,44 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_wwdg.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the WWDG
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_WWDG_H
|
||||||
|
#define __CH32V30x_WWDG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* WWDG_Prescaler */
|
||||||
|
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||||
|
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||||
|
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||||
|
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||||
|
|
||||||
|
|
||||||
|
void WWDG_DeInit(void);
|
||||||
|
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||||
|
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||||
|
void WWDG_EnableIT(void);
|
||||||
|
void WWDG_SetCounter(uint8_t Counter);
|
||||||
|
void WWDG_Enable(uint8_t Counter);
|
||||||
|
FlagStatus WWDG_GetFlagStatus(void);
|
||||||
|
void WWDG_ClearFlag(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,244 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_bkp.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file provides all the BKP firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_bkp.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* BKP registers bit mask */
|
||||||
|
|
||||||
|
/* OCTLR register bit mask */
|
||||||
|
#define OCTLR_CAL_MASK ((uint16_t)0xFF80)
|
||||||
|
#define OCTLR_MASK ((uint16_t)0xFC7F)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the BKP peripheral registers to their default reset values.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC_BackupResetCmd(ENABLE);
|
||||||
|
RCC_BackupResetCmd(DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_TamperPinLevelConfig
|
||||||
|
*
|
||||||
|
* @brief Configures the Tamper Pin active level.
|
||||||
|
*
|
||||||
|
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
|
||||||
|
* BKP_TamperPinLevel_High - Tamper pin active on high level.
|
||||||
|
* BKP_TamperPinLevel_Low - Tamper pin active on low level.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
|
||||||
|
{
|
||||||
|
if(BKP_TamperPinLevel)
|
||||||
|
{
|
||||||
|
BKP->TPCTLR |= (1 << 1);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
BKP->TPCTLR &= ~(1 << 1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_TamperPinCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the Tamper Pin activation.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_TamperPinCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
BKP->TPCTLR |= (1 << 0);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
BKP->TPCTLR &= ~(1 << 0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the Tamper Pin Interrupt.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_ITConfig(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
BKP->TPCSR |= (1 << 2);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
BKP->TPCSR &= ~(1 << 2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_RTCOutputConfig
|
||||||
|
*
|
||||||
|
* @brief Select the RTC output source to output on the Tamper pin.
|
||||||
|
*
|
||||||
|
* @param BKP_RTCOutputSource - specifies the RTC output source.
|
||||||
|
* BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
|
||||||
|
* BKP_RTCOutputSource_CalibClock - output the RTC clock with
|
||||||
|
* frequency divided by 64 on the Tamper pin.
|
||||||
|
* BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
|
||||||
|
* on the Tamper pin.
|
||||||
|
* BKP_RTCOutputSource_Second - output the RTC Second pulse
|
||||||
|
* signal on the Tamper pin.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = BKP->OCTLR;
|
||||||
|
tmpreg &= OCTLR_MASK;
|
||||||
|
tmpreg |= BKP_RTCOutputSource;
|
||||||
|
BKP->OCTLR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_SetRTCCalibrationValue
|
||||||
|
*
|
||||||
|
* @brief Sets RTC Clock Calibration value.
|
||||||
|
*
|
||||||
|
* @param CalibrationValue - specifies the RTC Clock Calibration value.
|
||||||
|
* This parameter must be a number between 0 and 0x7F.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = BKP->OCTLR;
|
||||||
|
tmpreg &= OCTLR_CAL_MASK;
|
||||||
|
tmpreg |= CalibrationValue;
|
||||||
|
BKP->OCTLR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_WriteBackupRegister
|
||||||
|
*
|
||||||
|
* @brief Writes user data to the specified Data Backup Register.
|
||||||
|
*
|
||||||
|
* @param BKP_DR - specifies the Data Backup Register.
|
||||||
|
* Data - data to write.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)BKP_BASE;
|
||||||
|
tmp += BKP_DR;
|
||||||
|
*(__IO uint32_t *)tmp = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_ReadBackupRegister
|
||||||
|
*
|
||||||
|
* @brief Reads data from the specified Data Backup Register.
|
||||||
|
*
|
||||||
|
* @param BKP_DR - specifies the Data Backup Register.
|
||||||
|
* This parameter can be BKP_DRx where x=[1, 42].
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)BKP_BASE;
|
||||||
|
tmp += BKP_DR;
|
||||||
|
|
||||||
|
return (*(__IO uint16_t *)tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the Tamper Pin Event flag is set or not.
|
||||||
|
*
|
||||||
|
* @return FlagStatus - SET or RESET.
|
||||||
|
*/
|
||||||
|
FlagStatus BKP_GetFlagStatus(void)
|
||||||
|
{
|
||||||
|
if(BKP->TPCSR & (1 << 8))
|
||||||
|
{
|
||||||
|
return SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears Tamper Pin Event pending flag.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_ClearFlag(void)
|
||||||
|
{
|
||||||
|
BKP->TPCSR |= BKP_CTE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
|
||||||
|
*
|
||||||
|
* @return ITStatus - SET or RESET.
|
||||||
|
*/
|
||||||
|
ITStatus BKP_GetITStatus(void)
|
||||||
|
{
|
||||||
|
if(BKP->TPCSR & (1 << 9))
|
||||||
|
{
|
||||||
|
return SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears Tamper Pin Interrupt pending bit.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_ClearITPendingBit(void)
|
||||||
|
{
|
||||||
|
BKP->TPCSR |= BKP_CTI;
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,100 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_crc.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the CRC firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_crc.h"
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_ResetDR
|
||||||
|
*
|
||||||
|
* @brief Resets the CRC Data register (DR).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void CRC_ResetDR(void)
|
||||||
|
{
|
||||||
|
CRC->CTLR = CRC_CTLR_RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_CalcCRC
|
||||||
|
*
|
||||||
|
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||||
|
*
|
||||||
|
* @param Data - data word(32-bit) to compute its CRC.
|
||||||
|
*
|
||||||
|
* @return 32-bit CRC.
|
||||||
|
*/
|
||||||
|
uint32_t CRC_CalcCRC(uint32_t Data)
|
||||||
|
{
|
||||||
|
CRC->DATAR = Data;
|
||||||
|
|
||||||
|
return (CRC->DATAR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_CalcBlockCRC
|
||||||
|
*
|
||||||
|
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||||
|
*
|
||||||
|
* @param pBuffer - pointer to the buffer containing the data to be computed.
|
||||||
|
* BufferLength - length of the buffer to be computed.
|
||||||
|
*
|
||||||
|
* @return 32-bit CRC.
|
||||||
|
*/
|
||||||
|
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
|
||||||
|
{
|
||||||
|
uint32_t index = 0;
|
||||||
|
|
||||||
|
for(index = 0; index < BufferLength; index++)
|
||||||
|
{
|
||||||
|
CRC->DATAR = pBuffer[index];
|
||||||
|
}
|
||||||
|
|
||||||
|
return (CRC->DATAR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_GetCRC
|
||||||
|
*
|
||||||
|
* @brief Returns the current CRC value.
|
||||||
|
*
|
||||||
|
* @return 32-bit CRC.
|
||||||
|
*/
|
||||||
|
uint32_t CRC_GetCRC(void)
|
||||||
|
{
|
||||||
|
return (CRC->DATAR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_SetIDRegister
|
||||||
|
*
|
||||||
|
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||||
|
*
|
||||||
|
* @param IDValue - 8-bit value to be stored in the ID register.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void CRC_SetIDRegister(uint8_t IDValue)
|
||||||
|
{
|
||||||
|
CRC->IDATAR = IDValue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_GetIDRegister
|
||||||
|
*
|
||||||
|
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
|
||||||
|
*
|
||||||
|
* @return 8-bit value of the ID register.
|
||||||
|
*/
|
||||||
|
uint8_t CRC_GetIDRegister(void)
|
||||||
|
{
|
||||||
|
return (CRC->IDATAR);
|
||||||
|
}
|
||||||
@@ -0,0 +1,304 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dac.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the DAC firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_dac.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* CTLR register Mask */
|
||||||
|
#define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE)
|
||||||
|
|
||||||
|
/* DAC Dual Channels SWTR masks */
|
||||||
|
#define DUAL_SWTR_SET ((uint32_t)0x00000003)
|
||||||
|
#define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC)
|
||||||
|
|
||||||
|
/* DHR registers offsets */
|
||||||
|
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
||||||
|
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
|
||||||
|
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
|
||||||
|
|
||||||
|
/* DOR register offset */
|
||||||
|
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the DAC peripheral according to the specified parameters in
|
||||||
|
* the DAC_InitStruct.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
* DAC_InitStruct - pointer to a DAC_InitTypeDef structure.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||||
|
|
||||||
|
tmpreg1 = DAC->CTLR;
|
||||||
|
tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel);
|
||||||
|
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
|
||||||
|
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
|
||||||
|
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||||
|
DAC->CTLR = tmpreg1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each DAC_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct)
|
||||||
|
{
|
||||||
|
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
||||||
|
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
||||||
|
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
|
||||||
|
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified DAC channel.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
* NewState - new state of the DAC channel(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DAC->CTLR |= (DAC_EN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DAC->CTLR &= ~(DAC_EN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_DMACmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified DAC channel DMA request.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
* NewState - new state of the DAC channel(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_SoftwareTriggerCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the selected DAC channel software trigger.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
* NewState - new state of the DAC channel(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_DualSoftwareTriggerCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the two DAC channel software trigger.
|
||||||
|
*
|
||||||
|
* @param NewState - new state of the DAC channel(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DAC->SWTR |= DUAL_SWTR_SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DAC->SWTR &= DUAL_SWTR_RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_WaveGenerationCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the selected DAC channel wave generation.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
* DAC_Wave - Specifies the wave type to enable or disable.
|
||||||
|
* DAC_Wave_Noise - noise wave generation
|
||||||
|
* DAC_Wave_Triangle - triangle wave generation
|
||||||
|
* NewState - new state of the DAC channel(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DAC->CTLR |= DAC_Wave << DAC_Channel;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DAC->CTLR &= ~(DAC_Wave << DAC_Channel);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_SetChannel1Data
|
||||||
|
*
|
||||||
|
* @brief Set the specified data holding register value for DAC channel1.
|
||||||
|
*
|
||||||
|
* @param DAC_Align - Specifies the data alignment for DAC channel1.
|
||||||
|
* DAC_Align_8b_R - 8bit right data alignment selected
|
||||||
|
* DAC_Align_12b_L - 12bit left data alignment selected
|
||||||
|
* DAC_Align_12b_R - 12bit right data alignment selected
|
||||||
|
* Data - Data to be loaded in the selected data holding register.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DHR12R1_OFFSET + DAC_Align;
|
||||||
|
|
||||||
|
*(__IO uint32_t *)tmp = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_SetChannel2Data
|
||||||
|
*
|
||||||
|
* @brief Set the specified data holding register value for DAC channel2.
|
||||||
|
*
|
||||||
|
* @param DAC_Align - Specifies the data alignment for DAC channel1.
|
||||||
|
* DAC_Align_8b_R - 8bit right data alignment selected
|
||||||
|
* DAC_Align_12b_L - 12bit left data alignment selected
|
||||||
|
* DAC_Align_12b_R - 12bit right data alignment selected
|
||||||
|
* Data - Data to be loaded in the selected data holding register.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DHR12R2_OFFSET + DAC_Align;
|
||||||
|
|
||||||
|
*(__IO uint32_t *)tmp = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_SetDualChannelData
|
||||||
|
*
|
||||||
|
* @brief Set the specified data holding register value for two DAC.
|
||||||
|
*
|
||||||
|
* @param DAC_Align - Specifies the data alignment for DAC channel1.
|
||||||
|
* DAC_Align_8b_R - 8bit right data alignment selected
|
||||||
|
* DAC_Align_12b_L - 12bit left data alignment selected
|
||||||
|
* DAC_Align_12b_R - 12bit right data alignment selected
|
||||||
|
* Data - Data to be loaded in the selected data holding register.
|
||||||
|
* Data1 - Data for DAC Channel1.
|
||||||
|
* Data2 - Data for DAC Channel2
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
||||||
|
{
|
||||||
|
uint32_t data = 0, tmp = 0;
|
||||||
|
|
||||||
|
if(DAC_Align == DAC_Align_8b_R)
|
||||||
|
{
|
||||||
|
data = ((uint32_t)Data2 << 8) | Data1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
data = ((uint32_t)Data2 << 16) | Data1;
|
||||||
|
}
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DHR12RD_OFFSET + DAC_Align;
|
||||||
|
|
||||||
|
*(__IO uint32_t *)tmp = data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_GetDataOutputValue
|
||||||
|
*
|
||||||
|
* @brief Returns the last data output value of the selected DAC channel.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||||
|
|
||||||
|
return (uint16_t)(*(__IO uint32_t *)tmp);
|
||||||
|
}
|
||||||
@@ -0,0 +1,129 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dbgmcu.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/05/28
|
||||||
|
* Description : This file provides all the DBGMCU firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_dbgmcu.h"
|
||||||
|
|
||||||
|
#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DBGMCU_GetREVID
|
||||||
|
*
|
||||||
|
* @brief Returns the device revision identifier.
|
||||||
|
*
|
||||||
|
* @return Revision identifier.
|
||||||
|
*/
|
||||||
|
uint32_t DBGMCU_GetREVID(void)
|
||||||
|
{
|
||||||
|
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DBGMCU_GetDEVID
|
||||||
|
*
|
||||||
|
* @brief Returns the device identifier.
|
||||||
|
*
|
||||||
|
* @return Device identifier.
|
||||||
|
*/
|
||||||
|
uint32_t DBGMCU_GetDEVID(void)
|
||||||
|
{
|
||||||
|
return ((*(uint32_t *)0x1FFFF704) >> 16);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_DEBUG_CR
|
||||||
|
*
|
||||||
|
* @brief Return the DEBUGE Control Register
|
||||||
|
*
|
||||||
|
* @return DEBUGE Control value
|
||||||
|
*/
|
||||||
|
uint32_t __get_DEBUG_CR(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__asm volatile("csrr %0,""0x7C0" : "=r"(result));
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_DEBUG_CR
|
||||||
|
*
|
||||||
|
* @brief Set the DEBUGE Control Register
|
||||||
|
*
|
||||||
|
* @param value - set DEBUGE Control value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_DEBUG_CR(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("csrw 0x7C0, %0" : : "r"(value));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DBGMCU_Config
|
||||||
|
*
|
||||||
|
* @brief Configures the specified peripheral and low power mode behavior
|
||||||
|
* when the MCU under Debug mode.
|
||||||
|
*
|
||||||
|
* @param DBGMCU_Periph - specifies the peripheral and low power mode.
|
||||||
|
* DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
|
||||||
|
* DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
|
||||||
|
* DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
|
||||||
|
* DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
uint32_t val;
|
||||||
|
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
__set_DEBUG_CR(DBGMCU_Periph);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
val = __get_DEBUG_CR();
|
||||||
|
val &= ~(uint32_t)DBGMCU_Periph;
|
||||||
|
__set_DEBUG_CR(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DBGMCU_GetCHIPID
|
||||||
|
*
|
||||||
|
* @brief Returns the CHIP identifier.
|
||||||
|
*
|
||||||
|
* @return Device identifier.
|
||||||
|
* ChipID List-
|
||||||
|
* CH32V303CBT6-0x303305x4
|
||||||
|
* CH32V303RBT6-0x303205x4
|
||||||
|
* CH32V303RCT6-0x303105x4
|
||||||
|
* CH32V303VCT6-0x303005x4
|
||||||
|
* CH32V305FBP6-0x305205x8
|
||||||
|
* CH32V305RBT6-0x305005x8
|
||||||
|
* CH32V305GBU6-0x305B05x8
|
||||||
|
* CH32V305CCT6-0x305C05x8
|
||||||
|
* CH32V307WCU6-0x307305x8
|
||||||
|
* CH32V307FBP6-0x307205x8
|
||||||
|
* CH32V307RCT6-0x307105x8
|
||||||
|
* CH32V307VCT6-0x307005x8
|
||||||
|
* CH32V317VCT6-0x3170B5X8
|
||||||
|
* CH32V317WCU6-0x3173B5X8
|
||||||
|
* CH32V317TCU6-0x3175B5X8
|
||||||
|
*/
|
||||||
|
uint32_t DBGMCU_GetCHIPID( void )
|
||||||
|
{
|
||||||
|
return( *( uint32_t * )0x1FFFF704 );
|
||||||
|
}
|
||||||
|
|
||||||
@@ -0,0 +1,692 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dma.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the DMA firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_dma.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* DMA1 Channelx interrupt pending bit masks */
|
||||||
|
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
|
||||||
|
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
|
||||||
|
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
|
||||||
|
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
|
||||||
|
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
|
||||||
|
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
|
||||||
|
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
|
||||||
|
|
||||||
|
/* DMA2 Channelx interrupt pending bit masks */
|
||||||
|
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
|
||||||
|
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
|
||||||
|
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
|
||||||
|
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
|
||||||
|
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
|
||||||
|
#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
|
||||||
|
#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
|
||||||
|
#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
|
||||||
|
#define DMA2_Channel9_IT_Mask ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9))
|
||||||
|
#define DMA2_Channel10_IT_Mask ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10))
|
||||||
|
#define DMA2_Channel11_IT_Mask ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11))
|
||||||
|
|
||||||
|
/* DMA2 FLAG mask */
|
||||||
|
#define FLAG_Mask ((uint32_t)0x10000000)
|
||||||
|
#define DMA2_EXTEN_FLAG_Mask ((uint32_t)0x20000000)
|
||||||
|
|
||||||
|
/* DMA registers Masks */
|
||||||
|
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the DMAy Channelx registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
|
||||||
|
DMAy_Channelx->CFGR = 0;
|
||||||
|
DMAy_Channelx->CNTR = 0;
|
||||||
|
DMAy_Channelx->PADDR = 0;
|
||||||
|
DMAy_Channelx->MADDR = 0;
|
||||||
|
if(DMAy_Channelx == DMA1_Channel1)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel2)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel3)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel4)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel5)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel6)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel7)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel1)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel2)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel3)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel4)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel5)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel6)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel6_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel7)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel7_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel8)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel9)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel10)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel11)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the DMAy Channelx according to the specified
|
||||||
|
* parameters in the DMA_InitStruct.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
|
||||||
|
* contains the configuration information for the specified DMA Channel.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = DMAy_Channelx->CFGR;
|
||||||
|
tmpreg &= CFGR_CLEAR_Mask;
|
||||||
|
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||||
|
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||||
|
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||||
|
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||||
|
|
||||||
|
DMAy_Channelx->CFGR = tmpreg;
|
||||||
|
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
|
||||||
|
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||||
|
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each DMA_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
|
||||||
|
* contains the configuration information for the specified DMA Channel.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
|
||||||
|
{
|
||||||
|
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||||
|
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||||
|
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||||
|
DMA_InitStruct->DMA_BufferSize = 0;
|
||||||
|
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||||
|
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||||
|
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||||
|
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||||
|
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||||
|
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||||
|
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified DMAy Channelx.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
* DMA_IT - specifies the DMA interrupts sources to be enabled
|
||||||
|
* or disabled.
|
||||||
|
* DMA_IT_TC - Transfer complete interrupt mask
|
||||||
|
* DMA_IT_HT - Half transfer interrupt mask
|
||||||
|
* DMA_IT_TE - Transfer error interrupt mask
|
||||||
|
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CFGR |= DMA_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CFGR &= ~DMA_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_SetCurrDataCounter
|
||||||
|
*
|
||||||
|
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
* DataNumber - The number of data units in the current DMAy Channelx
|
||||||
|
* transfer.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CNTR = DataNumber;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_GetCurrDataCounter
|
||||||
|
*
|
||||||
|
* @brief Returns the number of remaining data units in the current
|
||||||
|
* DMAy Channelx transfer.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
*
|
||||||
|
* @return DataNumber - The number of remaining data units in the current
|
||||||
|
* DMAy Channelx transfer.
|
||||||
|
*/
|
||||||
|
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
|
||||||
|
{
|
||||||
|
return ((uint16_t)(DMAy_Channelx->CNTR));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||||
|
*
|
||||||
|
* @param DMAy_FLAG - specifies the flag to check.
|
||||||
|
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
|
||||||
|
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
|
||||||
|
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
|
||||||
|
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
|
||||||
|
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
|
||||||
|
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
|
||||||
|
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
|
||||||
|
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
|
||||||
|
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
|
||||||
|
* DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
|
||||||
|
* DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
|
||||||
|
* DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
|
||||||
|
* DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL6 - DMA2 Channel6 global flag.
|
||||||
|
* DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL7 - DMA2 Channel7 global flag.
|
||||||
|
* DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL8 - DMA2 Channel8 global flag.
|
||||||
|
* DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL9 - DMA2 Channel9 global flag.
|
||||||
|
* DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL10 - DMA2 Channel10 global flag.
|
||||||
|
* DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL11 - DMA2 Channel11 global flag.
|
||||||
|
* DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag.
|
||||||
|
*
|
||||||
|
* @return The new state of DMAy_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
|
||||||
|
{
|
||||||
|
tmpreg = DMA2->INTFR;
|
||||||
|
}
|
||||||
|
else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
|
||||||
|
{
|
||||||
|
tmpreg = DMA2_EXTEN->INTFR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmpreg = DMA1->INTFR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the DMAy Channelx's pending flags.
|
||||||
|
*
|
||||||
|
* @param DMAy_FLAG - specifies the flag to check.
|
||||||
|
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
|
||||||
|
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
|
||||||
|
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
|
||||||
|
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
|
||||||
|
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
|
||||||
|
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
|
||||||
|
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
|
||||||
|
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
|
||||||
|
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
|
||||||
|
* DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
|
||||||
|
* DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
|
||||||
|
* DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
|
||||||
|
* DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL6 - DMA2 Channel6 global flag.
|
||||||
|
* DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL7 - DMA2 Channel7 global flag.
|
||||||
|
* DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL8 - DMA2 Channel8 global flag.
|
||||||
|
* DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL9 - DMA2 Channel9 global flag.
|
||||||
|
* DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL10 - DMA2 Channel10 global flag.
|
||||||
|
* DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL11 - DMA2 Channel11 global flag.
|
||||||
|
* DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||||
|
{
|
||||||
|
if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR = DMAy_FLAG;
|
||||||
|
}
|
||||||
|
else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR = DMAy_FLAG;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DMA1->INTFCR = DMAy_FLAG;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified DMAy Channelx interrupt has
|
||||||
|
* occurred or not.
|
||||||
|
*
|
||||||
|
* @param DMAy_IT - specifies the DMAy interrupt source to check.
|
||||||
|
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
|
||||||
|
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
|
||||||
|
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
|
||||||
|
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
|
||||||
|
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
|
||||||
|
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
|
||||||
|
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
|
||||||
|
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
|
||||||
|
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
|
||||||
|
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
|
||||||
|
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
|
||||||
|
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
|
||||||
|
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
|
||||||
|
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
|
||||||
|
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
|
||||||
|
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
|
||||||
|
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
|
||||||
|
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
|
||||||
|
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
|
||||||
|
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
|
||||||
|
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
|
||||||
|
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
|
||||||
|
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
|
||||||
|
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
|
||||||
|
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
|
||||||
|
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
|
||||||
|
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
|
||||||
|
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
|
||||||
|
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
|
||||||
|
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
|
||||||
|
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
|
||||||
|
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
|
||||||
|
* DMA2_IT_GL2 - DMA2 Channel2 global flag.
|
||||||
|
* DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
|
||||||
|
* DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
|
||||||
|
* DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
|
||||||
|
* DMA2_IT_GL3 - DMA2 Channel3 global flag.
|
||||||
|
* DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
|
||||||
|
* DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
|
||||||
|
* DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
|
||||||
|
* DMA2_IT_GL4 - DMA2 Channel4 global flag.
|
||||||
|
* DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
|
||||||
|
* DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
|
||||||
|
* DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
|
||||||
|
* DMA2_IT_GL5 - DMA2 Channel5 global flag.
|
||||||
|
* DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
|
||||||
|
* DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
|
||||||
|
* DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
|
||||||
|
* DMA2_IT_GL6 - DMA2 Channel6 global flag.
|
||||||
|
* DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag.
|
||||||
|
* DMA2_IT_HT6 - DMA2 Channel6 half transfer flag.
|
||||||
|
* DMA2_IT_TE6 - DMA2 Channel6 transfer error flag.
|
||||||
|
* DMA2_IT_GL7 - DMA2 Channel7 global flag.
|
||||||
|
* DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag.
|
||||||
|
* DMA2_IT_HT7 - DMA2 Channel7 half transfer flag.
|
||||||
|
* DMA2_IT_TE7 - DMA2 Channel7 transfer error flag.
|
||||||
|
* DMA2_IT_GL8 - DMA2 Channel8 global flag.
|
||||||
|
* DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag.
|
||||||
|
* DMA2_IT_HT8 - DMA2 Channel8 half transfer flag.
|
||||||
|
* DMA2_IT_TE8 - DMA2 Channel8 transfer error flag.
|
||||||
|
* DMA2_IT_GL9 - DMA2 Channel9 global flag.
|
||||||
|
* DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag.
|
||||||
|
* DMA2_IT_HT9 - DMA2 Channel9 half transfer flag.
|
||||||
|
* DMA2_IT_TE9 - DMA2 Channel9 transfer error flag.
|
||||||
|
* DMA2_IT_GL10 - DMA2 Channel10 global flag.
|
||||||
|
* DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag.
|
||||||
|
* DMA2_IT_HT10 - DMA2 Channel10 half transfer flag.
|
||||||
|
* DMA2_IT_TE10 - DMA2 Channel10 transfer error flag.
|
||||||
|
* DMA2_IT_GL11 - DMA2 Channel11 global flag.
|
||||||
|
* DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag.
|
||||||
|
* DMA2_IT_HT11 - DMA2 Channel11 half transfer flag.
|
||||||
|
* DMA2_IT_TE11 - DMA2 Channel11 transfer error flag.
|
||||||
|
*
|
||||||
|
* @return The new state of DMAy_IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
if((DMAy_IT & FLAG_Mask) == FLAG_Mask)
|
||||||
|
{
|
||||||
|
tmpreg = DMA2->INTFR;
|
||||||
|
}
|
||||||
|
else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
|
||||||
|
{
|
||||||
|
tmpreg = DMA2_EXTEN->INTFR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmpreg = DMA1->INTFR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||||
|
*
|
||||||
|
* @param DMAy_IT - specifies the DMAy interrupt source to check.
|
||||||
|
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
|
||||||
|
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
|
||||||
|
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
|
||||||
|
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
|
||||||
|
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
|
||||||
|
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
|
||||||
|
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
|
||||||
|
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
|
||||||
|
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
|
||||||
|
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
|
||||||
|
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
|
||||||
|
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
|
||||||
|
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
|
||||||
|
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
|
||||||
|
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
|
||||||
|
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
|
||||||
|
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
|
||||||
|
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
|
||||||
|
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
|
||||||
|
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
|
||||||
|
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
|
||||||
|
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
|
||||||
|
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
|
||||||
|
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
|
||||||
|
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
|
||||||
|
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
|
||||||
|
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
|
||||||
|
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
|
||||||
|
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
|
||||||
|
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
|
||||||
|
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
|
||||||
|
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
|
||||||
|
* DMA2_IT_GL2 - DMA2 Channel2 global flag.
|
||||||
|
* DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
|
||||||
|
* DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
|
||||||
|
* DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
|
||||||
|
* DMA2_IT_GL3 - DMA2 Channel3 global flag.
|
||||||
|
* DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
|
||||||
|
* DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
|
||||||
|
* DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
|
||||||
|
* DMA2_IT_GL4 - DMA2 Channel4 global flag.
|
||||||
|
* DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
|
||||||
|
* DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
|
||||||
|
* DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
|
||||||
|
* DMA2_IT_GL5 - DMA2 Channel5 global flag.
|
||||||
|
* DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
|
||||||
|
* DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
|
||||||
|
* DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
|
||||||
|
* DMA2_IT_GL6 - DMA2 Channel6 global flag.
|
||||||
|
* DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag.
|
||||||
|
* DMA2_IT_HT6 - DMA2 Channel6 half transfer flag.
|
||||||
|
* DMA2_IT_TE6 - DMA2 Channel6 transfer error flag.
|
||||||
|
* DMA2_IT_GL7 - DMA2 Channel7 global flag.
|
||||||
|
* DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag.
|
||||||
|
* DMA2_IT_HT7 - DMA2 Channel7 half transfer flag.
|
||||||
|
* DMA2_IT_TE7 - DMA2 Channel7 transfer error flag.
|
||||||
|
* DMA2_IT_GL8 - DMA2 Channel8 global flag.
|
||||||
|
* DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag.
|
||||||
|
* DMA2_IT_HT8 - DMA2 Channel8 half transfer flag.
|
||||||
|
* DMA2_IT_TE8 - DMA2 Channel8 transfer error flag.
|
||||||
|
* DMA2_IT_GL9 - DMA2 Channel9 global flag.
|
||||||
|
* DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag.
|
||||||
|
* DMA2_IT_HT9 - DMA2 Channel9 half transfer flag.
|
||||||
|
* DMA2_IT_TE9 - DMA2 Channel9 transfer error flag.
|
||||||
|
* DMA2_IT_GL10 - DMA2 Channel10 global flag.
|
||||||
|
* DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag.
|
||||||
|
* DMA2_IT_HT10 - DMA2 Channel10 half transfer flag.
|
||||||
|
* DMA2_IT_TE10 - DMA2 Channel10 transfer error flag.
|
||||||
|
* DMA2_IT_GL11 - DMA2 Channel11 global flag.
|
||||||
|
* DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag.
|
||||||
|
* DMA2_IT_HT11 - DMA2 Channel11 half transfer flag.
|
||||||
|
* DMA2_IT_TE11 - DMA2 Channel11 transfer error flag.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||||
|
{
|
||||||
|
if((DMAy_IT & FLAG_Mask) == FLAG_Mask)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR = DMAy_IT;
|
||||||
|
}
|
||||||
|
else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR = DMAy_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DMA1->INTFCR = DMAy_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,135 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dvp.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the DVP firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_dvp.h"
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DVP_INTCfg
|
||||||
|
*
|
||||||
|
* @brief DVP interrupt configuration
|
||||||
|
*
|
||||||
|
* @param s - interrupt enable
|
||||||
|
* ENABLE
|
||||||
|
* DISABLE
|
||||||
|
* i - interrupt type
|
||||||
|
* RB_DVP_IE_STP_FRM
|
||||||
|
* RB_DVP_IE_FIFO_OV
|
||||||
|
* RB_DVP_IE_FRM_DONE
|
||||||
|
* RB_DVP_IE_ROW_DONE
|
||||||
|
* RB_DVP_IE_STR_FRM
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DVP_INTCfg(uint8_t s, uint8_t i)
|
||||||
|
{
|
||||||
|
if(s)
|
||||||
|
{
|
||||||
|
DVP->IER |= i;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DVP->IER &= ~i;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DVP_Mode
|
||||||
|
*
|
||||||
|
* @brief DVP mode
|
||||||
|
*
|
||||||
|
* @param s - data bit width
|
||||||
|
* RB_DVP_D8_MOD
|
||||||
|
* RB_DVP_D10_MOD
|
||||||
|
* RB_DVP_D12_MOD
|
||||||
|
* i - interrupt type
|
||||||
|
* Video_Mode
|
||||||
|
* JPEG_Mode
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i)
|
||||||
|
{
|
||||||
|
DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD;
|
||||||
|
|
||||||
|
if(s)
|
||||||
|
{
|
||||||
|
DVP->CR0 |= s;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DVP->CR0 &= ~(3 << 4);
|
||||||
|
}
|
||||||
|
|
||||||
|
if(i)
|
||||||
|
{
|
||||||
|
DVP->CR0 |= RB_DVP_JPEG;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DVP->CR0 &= ~RB_DVP_JPEG;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DVP_Cfg
|
||||||
|
*
|
||||||
|
* @brief DVP configuration
|
||||||
|
*
|
||||||
|
* @param s - DMA enable control
|
||||||
|
* DVP_DMA_Enable
|
||||||
|
* DVP_DMA_Disable
|
||||||
|
* i - DVP all clear
|
||||||
|
* DVP_FLAG_FIFO_RESET_Enable
|
||||||
|
* DVP_FLAG_FIFO_RESET_Disable
|
||||||
|
* j - receive reset enable
|
||||||
|
* DVP_RX_RESET_Enable
|
||||||
|
* DVP_RX_RESET_Disable
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j)
|
||||||
|
{
|
||||||
|
switch(s)
|
||||||
|
{
|
||||||
|
case DVP_DMA_Enable:
|
||||||
|
DVP->CR1 |= RB_DVP_DMA_EN;
|
||||||
|
break;
|
||||||
|
case DVP_DMA_Disable:
|
||||||
|
DVP->CR1 &= ~RB_DVP_DMA_EN;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch(i)
|
||||||
|
{
|
||||||
|
case DVP_RX_RESET_Enable:
|
||||||
|
DVP->CR1 |= RB_DVP_ALL_CLR;
|
||||||
|
break;
|
||||||
|
case DVP_RX_RESET_Disable:
|
||||||
|
DVP->CR1 &= ~RB_DVP_ALL_CLR;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch(j)
|
||||||
|
{
|
||||||
|
case DVP_RX_RESET_Enable:
|
||||||
|
DVP->CR1 |= RB_DVP_RCV_CLR;
|
||||||
|
break;
|
||||||
|
case DVP_RX_RESET_Disable:
|
||||||
|
DVP->CR1 &= ~RB_DVP_RCV_CLR;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,182 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_exti.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the EXTI firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_exti.h"
|
||||||
|
|
||||||
|
/* No interrupt selected */
|
||||||
|
#define EXTI_LINENONE ((uint32_t)0x00000)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the EXTI peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void EXTI_DeInit(void)
|
||||||
|
{
|
||||||
|
EXTI->INTENR = 0x00000000;
|
||||||
|
EXTI->EVENR = 0x00000000;
|
||||||
|
EXTI->RTENR = 0x00000000;
|
||||||
|
EXTI->FTENR = 0x00000000;
|
||||||
|
EXTI->INTFR = 0x000FFFFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the EXTI peripheral according to the specified
|
||||||
|
* parameters in the EXTI_InitStruct.
|
||||||
|
*
|
||||||
|
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)EXTI_BASE;
|
||||||
|
if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||||
|
{
|
||||||
|
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||||
|
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||||
|
{
|
||||||
|
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp = (uint32_t)EXTI_BASE;
|
||||||
|
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||||
|
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||||
|
*(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||||
|
*
|
||||||
|
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
|
||||||
|
{
|
||||||
|
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||||
|
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||||
|
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||||
|
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_GenerateSWInterrupt
|
||||||
|
*
|
||||||
|
* @brief Generates a Software interrupt.
|
||||||
|
*
|
||||||
|
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
EXTI->SWIEVR |= EXTI_Line;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||||
|
*
|
||||||
|
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||||
|
*
|
||||||
|
* @return The new state of EXTI_Line (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the EXTI's line pending flags.
|
||||||
|
*
|
||||||
|
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
EXTI->INTFR = EXTI_Line;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||||
|
*
|
||||||
|
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||||
|
*
|
||||||
|
* @return The new state of EXTI_Line (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint32_t enablestatus = 0;
|
||||||
|
|
||||||
|
enablestatus = EXTI->INTENR & EXTI_Line;
|
||||||
|
if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the EXTI's line pending bits.
|
||||||
|
*
|
||||||
|
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
EXTI->INTFR = EXTI_Line;
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,378 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_fsmc.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.1
|
||||||
|
* Date : 2025/04/06
|
||||||
|
* Description : This file provides all the FSMC firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_fsmc.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* FSMC BCRx Mask */
|
||||||
|
#define BCR_MBKEN_Set ((uint32_t)0x00000001)
|
||||||
|
#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
|
||||||
|
#define BCR_FACCEN_Set ((uint32_t)0x00000040)
|
||||||
|
|
||||||
|
/* FSMC PCRx Mask */
|
||||||
|
#define PCR_PBKEN_Set ((uint32_t)0x00000004)
|
||||||
|
#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
|
||||||
|
#define PCR_ECCEN_Set ((uint32_t)0x00000040)
|
||||||
|
#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
|
||||||
|
#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NORSRAMDeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank-
|
||||||
|
* FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
|
||||||
|
}
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
|
||||||
|
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NANDDeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the FSMC NAND Banks registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank -
|
||||||
|
* FSMC_Bank2_NAND - FSMC Bank2 NAND.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 = 0x00000018;
|
||||||
|
FSMC_Bank2->SR2 = 0x00000040;
|
||||||
|
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
|
||||||
|
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NORSRAMInit
|
||||||
|
*
|
||||||
|
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
|
||||||
|
* parameters in the FSMC_NORSRAMInitStruct.
|
||||||
|
*
|
||||||
|
* @param SMC_NORSRAMInitStruct:pointer to a FSMC_NORSRAMInitTypeDef
|
||||||
|
* structure that contains the configuration information for the FSMC NOR/SRAM
|
||||||
|
* specified Banks.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||||
|
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
|
||||||
|
|
||||||
|
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
|
||||||
|
}
|
||||||
|
|
||||||
|
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] =
|
||||||
|
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
|
||||||
|
|
||||||
|
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
|
||||||
|
{
|
||||||
|
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||||
|
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NANDInit
|
||||||
|
*
|
||||||
|
* @brief Initializes the FSMC NAND Banks according to the specified
|
||||||
|
* parameters in the FSMC_NANDInitStruct.
|
||||||
|
*
|
||||||
|
* @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef
|
||||||
|
* structure that contains the configuration information for the FSMC
|
||||||
|
* NAND specified Banks.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
|
||||||
|
|
||||||
|
tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
|
||||||
|
PCR_MemoryType_NAND |
|
||||||
|
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECC |
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECCPageSize |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
|
||||||
|
|
||||||
|
tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||||
|
|
||||||
|
tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||||
|
|
||||||
|
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 = tmppcr;
|
||||||
|
FSMC_Bank2->PMEM2 = tmppmem;
|
||||||
|
FSMC_Bank2->PATT2 = tmppatt;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NORSRAMStructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param FSMC_NORSRAMInitStruct - pointer to a FSMC_NORSRAMInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
|
||||||
|
{
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NANDStructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each FSMC_NANDInitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
|
||||||
|
{
|
||||||
|
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
|
||||||
|
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
||||||
|
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
|
||||||
|
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||||||
|
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NORSRAMCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank - specifies the FSMC Bank to be used
|
||||||
|
* FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1
|
||||||
|
* FSMC_Bank1_NORSRAM2 - FSMC Bank1 NOR/SRAM2
|
||||||
|
* FSMC_Bank1_NORSRAM3 - FSMC Bank1 NOR/SRAM3
|
||||||
|
* FSMC_Bank1_NORSRAM4 - FSMC Bank1 NOR/SRAM4
|
||||||
|
* NewState:ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NANDCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified NAND Memory Bank.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank - specifies the FSMC Bank to be used
|
||||||
|
* FSMC_Bank2_NAND - FSMC Bank2 NAND
|
||||||
|
* NewStat - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NANDECCCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the FSMC NAND ECC feature.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank - specifies the FSMC Bank to be used
|
||||||
|
* FSMC_Bank2_NAND - FSMC Bank2 NAND
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_GetECC
|
||||||
|
*
|
||||||
|
* @brief Returns the error correction code register value.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank - specifies the FSMC Bank to be used
|
||||||
|
* FSMC_Bank2_NAND - FSMC Bank2 NAND
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return eccval - The Error Correction Code (ECC) value.
|
||||||
|
*/
|
||||||
|
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
|
||||||
|
{
|
||||||
|
uint32_t eccval = 0x00000000;
|
||||||
|
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
eccval = FSMC_Bank2->ECCR2;
|
||||||
|
}
|
||||||
|
|
||||||
|
return (eccval);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified FSMC flag is set or not.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank - specifies the FSMC Bank to be used
|
||||||
|
* FSMC_Bank2_NAND - FSMC Bank2 NAND
|
||||||
|
* FSMC_FLAG - specifies the flag to check.
|
||||||
|
* FSMC_FLAG_FEMPT - Fifo empty Flag.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return FlagStatus - The new state of FSMC_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
uint32_t tmpsr = 0x00000000;
|
||||||
|
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
tmpsr = FSMC_Bank2->SR2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if((tmpsr & FSMC_FLAG) != (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
@@ -0,0 +1,895 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_gpio.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/05/06
|
||||||
|
* Description : This file provides all the GPIO firmware functions.
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_gpio.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* MASK */
|
||||||
|
#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
|
||||||
|
#define LSB_MASK ((uint16_t)0xFFFF)
|
||||||
|
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
|
||||||
|
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
|
||||||
|
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
|
||||||
|
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the GPIOx peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_DeInit(GPIO_TypeDef *GPIOx)
|
||||||
|
{
|
||||||
|
if(GPIOx == GPIOA)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
|
||||||
|
}
|
||||||
|
else if(GPIOx == GPIOB)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
|
||||||
|
}
|
||||||
|
else if(GPIOx == GPIOC)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
|
||||||
|
}
|
||||||
|
else if(GPIOx == GPIOD)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
|
||||||
|
}
|
||||||
|
else if(GPIOx == GPIOE)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_AFIODeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the Alternate Functions (remap, event control
|
||||||
|
* and EXTI configuration) registers to their default reset values.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_AFIODeInit(void)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_Init
|
||||||
|
*
|
||||||
|
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
|
||||||
|
uint32_t tmpreg = 0x00, pinmask = 0x00;
|
||||||
|
|
||||||
|
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
|
||||||
|
|
||||||
|
if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
|
||||||
|
{
|
||||||
|
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
|
||||||
|
{
|
||||||
|
tmpreg = GPIOx->CFGLR;
|
||||||
|
|
||||||
|
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||||
|
{
|
||||||
|
pos = ((uint32_t)0x01) << pinpos;
|
||||||
|
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||||
|
|
||||||
|
if(currentpin == pos)
|
||||||
|
{
|
||||||
|
pos = pinpos << 2;
|
||||||
|
pinmask = ((uint32_t)0x0F) << pos;
|
||||||
|
tmpreg &= ~pinmask;
|
||||||
|
tmpreg |= (currentmode << pos);
|
||||||
|
|
||||||
|
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||||
|
{
|
||||||
|
GPIOx->BCR = (((uint32_t)0x01) << pinpos);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||||
|
{
|
||||||
|
GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
GPIOx->CFGLR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(GPIO_InitStruct->GPIO_Pin > 0x00FF)
|
||||||
|
{
|
||||||
|
tmpreg = GPIOx->CFGHR;
|
||||||
|
|
||||||
|
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||||
|
{
|
||||||
|
pos = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||||
|
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
|
||||||
|
|
||||||
|
if(currentpin == pos)
|
||||||
|
{
|
||||||
|
pos = pinpos << 2;
|
||||||
|
pinmask = ((uint32_t)0x0F) << pos;
|
||||||
|
tmpreg &= ~pinmask;
|
||||||
|
tmpreg |= (currentmode << pos);
|
||||||
|
|
||||||
|
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||||
|
{
|
||||||
|
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||||
|
}
|
||||||
|
|
||||||
|
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||||
|
{
|
||||||
|
GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
GPIOx->CFGHR = tmpreg;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each GPIO_InitStruct member with its default
|
||||||
|
*
|
||||||
|
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
|
||||||
|
* which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
|
||||||
|
{
|
||||||
|
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||||
|
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||||
|
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ReadInputDataBit
|
||||||
|
*
|
||||||
|
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @param GPIO_Pin - specifies the port bit to read.
|
||||||
|
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return The input port pin value.
|
||||||
|
*/
|
||||||
|
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
uint8_t bitstatus = 0x00;
|
||||||
|
|
||||||
|
if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ReadInputData
|
||||||
|
*
|
||||||
|
* @brief Reads the specified GPIO input data port.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @return The output port pin value.
|
||||||
|
*/
|
||||||
|
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
|
||||||
|
{
|
||||||
|
return ((uint16_t)GPIOx->INDR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ReadOutputDataBit
|
||||||
|
*
|
||||||
|
* @brief Reads the specified output data port bit.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* GPIO_Pin - specifies the port bit to read.
|
||||||
|
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
uint8_t bitstatus = 0x00;
|
||||||
|
|
||||||
|
if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ReadOutputData
|
||||||
|
*
|
||||||
|
* @brief Reads the specified GPIO output data port.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @return GPIO output port pin value.
|
||||||
|
*/
|
||||||
|
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
|
||||||
|
{
|
||||||
|
return ((uint16_t)GPIOx->OUTDR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_SetBits
|
||||||
|
*
|
||||||
|
* @brief Sets the selected data port bits.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* GPIO_Pin - specifies the port bits to be written.
|
||||||
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
GPIOx->BSHR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ResetBits
|
||||||
|
*
|
||||||
|
* @brief Clears the selected data port bits.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* GPIO_Pin - specifies the port bits to be written.
|
||||||
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
GPIOx->BCR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_WriteBit
|
||||||
|
*
|
||||||
|
* @brief Sets or clears the selected data port bit.
|
||||||
|
*
|
||||||
|
* @param GPIO_Pin - specifies the port bit to be written.
|
||||||
|
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||||
|
* BitVal - specifies the value to be written to the selected bit.
|
||||||
|
* Bit_RESET - to clear the port pin.
|
||||||
|
* Bit_SET - to set the port pin.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||||
|
{
|
||||||
|
if(BitVal != Bit_RESET)
|
||||||
|
{
|
||||||
|
GPIOx->BSHR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
GPIOx->BCR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_Write
|
||||||
|
*
|
||||||
|
* @brief Writes data to the specified GPIO data port.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* PortVal - specifies the value to be written to the port output data register.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
|
||||||
|
{
|
||||||
|
GPIOx->OUTDR = PortVal;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_PinLockConfig
|
||||||
|
*
|
||||||
|
* @brief Locks GPIO Pins configuration registers.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* GPIO_Pin - specifies the port bit to be written.
|
||||||
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x00010000;
|
||||||
|
|
||||||
|
tmp |= GPIO_Pin;
|
||||||
|
GPIOx->LCKR = tmp;
|
||||||
|
GPIOx->LCKR = GPIO_Pin;
|
||||||
|
GPIOx->LCKR = tmp;
|
||||||
|
tmp = GPIOx->LCKR;
|
||||||
|
tmp = GPIOx->LCKR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_EventOutputConfig
|
||||||
|
*
|
||||||
|
* @brief Selects the GPIO pin used as Event output.
|
||||||
|
*
|
||||||
|
* @param GPIO_PortSource - selects the GPIO port to be used as source
|
||||||
|
* for Event output.
|
||||||
|
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
|
||||||
|
* GPIO_PinSource - specifies the pin for the Event output.
|
||||||
|
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0x00;
|
||||||
|
|
||||||
|
tmpreg = AFIO->ECR;
|
||||||
|
tmpreg &= ECR_PORTPINCONFIG_MASK;
|
||||||
|
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
|
||||||
|
tmpreg |= GPIO_PinSource;
|
||||||
|
AFIO->ECR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_EventOutputCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the Event Output.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_EventOutputCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
AFIO->ECR |= (1 << 7);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
AFIO->ECR &= ~(1 << 7);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_PinRemapConfig
|
||||||
|
*
|
||||||
|
* @brief Changes the mapping of the specified pin.
|
||||||
|
*
|
||||||
|
* @param GPIO_Remap - selects the pin to remap.
|
||||||
|
* GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
|
||||||
|
* GPIO_Remap_SPI3 - SPI3 Alternate Function mapping(CH32V30X_D8,CH32V30X_D8C)
|
||||||
|
* GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
|
||||||
|
* GPIO_Remap_USART1 - USART1 Alternate Function mapping
|
||||||
|
* GPIO_Remap_USART2 - USART2 Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap1_USART3 - USART3 Partial1 Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
|
||||||
|
* GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
|
||||||
|
* GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
|
||||||
|
* GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
|
||||||
|
* GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping
|
||||||
|
* GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
|
||||||
|
* GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
|
||||||
|
* GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
|
||||||
|
* GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
|
||||||
|
* GPIO_Remap_ETH - Ethernet remapping
|
||||||
|
* GPIO_Remap_CAN2 - CAN2 remapping
|
||||||
|
* GPIO_Remap_MII_RMII_SEL - MII or RMII selection
|
||||||
|
* GPIO_Remap_SWJ_Disable - Full SWJ Disabled
|
||||||
|
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||||
|
* to TIM2 Internal Trigger 1 for calibration
|
||||||
|
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
|
||||||
|
* GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
|
||||||
|
* GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
|
||||||
|
* GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
|
||||||
|
|
||||||
|
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||||
|
{
|
||||||
|
tmpreg = AFIO->PCFR2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmpreg = AFIO->PCFR1;
|
||||||
|
}
|
||||||
|
|
||||||
|
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
|
||||||
|
tmp = GPIO_Remap & LSB_MASK;
|
||||||
|
|
||||||
|
/* Clear bit */
|
||||||
|
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||||
|
{ /* PCFR2 */
|
||||||
|
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */
|
||||||
|
{
|
||||||
|
tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10);
|
||||||
|
tmpreg &= ~tmp1;
|
||||||
|
}
|
||||||
|
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
|
||||||
|
{
|
||||||
|
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||||
|
tmpreg &= ~tmp1;
|
||||||
|
}
|
||||||
|
else /* [31:0] 1bit */
|
||||||
|
{
|
||||||
|
tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{ /* PCFR1 */
|
||||||
|
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */
|
||||||
|
{
|
||||||
|
tmpreg &= DBGAFR_SWJCFG_MASK;
|
||||||
|
AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
|
||||||
|
}
|
||||||
|
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
|
||||||
|
{
|
||||||
|
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||||
|
tmpreg &= ~tmp1;
|
||||||
|
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||||
|
}
|
||||||
|
else /* [31:0] 1bit */
|
||||||
|
{
|
||||||
|
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
|
||||||
|
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set bit */
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10));
|
||||||
|
}
|
||||||
|
|
||||||
|
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||||
|
{
|
||||||
|
AFIO->PCFR2 = tmpreg;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
AFIO->PCFR1 = tmpreg;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_EXTILineConfig
|
||||||
|
*
|
||||||
|
* @brief Selects the GPIO pin used as EXTI Line.
|
||||||
|
*
|
||||||
|
* @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
|
||||||
|
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
|
||||||
|
* GPIO_PinSource - specifies the EXTI line to be configured.
|
||||||
|
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x00;
|
||||||
|
|
||||||
|
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
|
||||||
|
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
|
||||||
|
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ETH_MediaInterfaceConfig
|
||||||
|
*
|
||||||
|
* @brief Selects the Ethernet media interface.
|
||||||
|
*
|
||||||
|
* @param GPIO_ETH_MediaInterface - specifies the Media Interface mode.
|
||||||
|
* GPIO_ETH_MediaInterface_MII - MII mode
|
||||||
|
* GPIO_ETH_MediaInterface_RMII - RMII mode
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
|
||||||
|
{
|
||||||
|
if(GPIO_ETH_MediaInterface)
|
||||||
|
{
|
||||||
|
AFIO->PCFR1 |= (1 << 23);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
AFIO->PCFR1 &= ~(1 << 23);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_IPD_Unused
|
||||||
|
*
|
||||||
|
* @brief Configure unused GPIO as input pull-down.
|
||||||
|
*
|
||||||
|
* @param none
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_IPD_Unused(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||||
|
uint32_t chip = 0;
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC|\
|
||||||
|
RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE, ENABLE);
|
||||||
|
chip = *( uint32_t * )0x1FFFF704 & (~0x000000F0);
|
||||||
|
switch(chip)
|
||||||
|
{
|
||||||
|
#ifdef CH32V30x_D8
|
||||||
|
case 0x30330504: //CH32V303CBT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30320504: //CH32V303RBT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30310504: //CH32V303RCT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30300504: //CH32V303VCT6
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
#elif defined (CH32V30x_D8C)
|
||||||
|
case 0x30520508: //CH32V305FBP6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x305C0508: //CH32V305CCT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30500508: //CH32V305RBT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30710508: //CH32V307RCT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30730508: //CH32V307WCU6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x3173B508: //CH32V317WCU6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x3175B508: //CH32V317TCU6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15\
|
||||||
|
|GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30700508: //CH32V307VCT6
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x3170B508: //CH32V317VCT6
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
default:
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,123 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_iwdg.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file provides all the IWDG firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_iwdg.h"
|
||||||
|
|
||||||
|
/* CTLR register bit mask */
|
||||||
|
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
|
||||||
|
#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_WriteAccessCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
|
||||||
|
*
|
||||||
|
* @param WDG_WriteAccess - new state of write access to IWDG_PSCR and
|
||||||
|
* IWDG_RLDR registers.
|
||||||
|
* IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
|
||||||
|
* IWDG_RLDR registers.
|
||||||
|
* IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
|
||||||
|
* and IWDG_RLDR registers.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
|
||||||
|
{
|
||||||
|
IWDG->CTLR = IWDG_WriteAccess;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_SetPrescaler
|
||||||
|
*
|
||||||
|
* @brief Sets IWDG Prescaler value.
|
||||||
|
*
|
||||||
|
* @param IWDG_Prescaler - specifies the IWDG Prescaler value.
|
||||||
|
* IWDG_Prescaler_4 - IWDG prescaler set to 4.
|
||||||
|
* IWDG_Prescaler_8 - IWDG prescaler set to 8.
|
||||||
|
* IWDG_Prescaler_16 - IWDG prescaler set to 16.
|
||||||
|
* IWDG_Prescaler_32 - IWDG prescaler set to 32.
|
||||||
|
* IWDG_Prescaler_64 - IWDG prescaler set to 64.
|
||||||
|
* IWDG_Prescaler_128 - IWDG prescaler set to 128.
|
||||||
|
* IWDG_Prescaler_256 - IWDG prescaler set to 256.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
|
||||||
|
{
|
||||||
|
IWDG->PSCR = IWDG_Prescaler;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_SetReload
|
||||||
|
*
|
||||||
|
* @brief Sets IWDG Reload value.
|
||||||
|
*
|
||||||
|
* @param Reload - specifies the IWDG Reload value.
|
||||||
|
* This parameter must be a number between 0 and 0x0FFF.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void IWDG_SetReload(uint16_t Reload)
|
||||||
|
{
|
||||||
|
IWDG->RLDR = Reload;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_ReloadCounter
|
||||||
|
*
|
||||||
|
* @brief Reloads IWDG counter with value defined in the reload register.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void IWDG_ReloadCounter(void)
|
||||||
|
{
|
||||||
|
IWDG->CTLR = CTLR_KEY_Reload;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_Enable
|
||||||
|
*
|
||||||
|
* @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void IWDG_Enable(void)
|
||||||
|
{
|
||||||
|
IWDG->CTLR = CTLR_KEY_Enable;
|
||||||
|
while((RCC->RSTSCKR & 0x2)==RESET);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified IWDG flag is set or not.
|
||||||
|
*
|
||||||
|
* @param IWDG_FLAG - specifies the flag to check.
|
||||||
|
* IWDG_FLAG_PVU - Prescaler Value Update on going.
|
||||||
|
* IWDG_FLAG_RVU - Reload Value Update on going.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
@@ -0,0 +1,105 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_misc.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file provides all the miscellaneous firmware functions .
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_misc.h"
|
||||||
|
|
||||||
|
__IO uint32_t NVIC_Priority_Group = 0;
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_PriorityGroupConfig
|
||||||
|
*
|
||||||
|
* @brief Configures the priority grouping - pre-emption priority and subpriority.
|
||||||
|
*
|
||||||
|
* @param NVIC_PriorityGroup - specifies the priority grouping bits length.
|
||||||
|
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
|
||||||
|
* 3 bits for subpriority
|
||||||
|
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
|
||||||
|
* 2 bits for subpriority
|
||||||
|
* NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
|
||||||
|
* 1 bits for subpriority
|
||||||
|
* NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
|
||||||
|
* 0 bits for subpriority
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||||
|
{
|
||||||
|
NVIC_Priority_Group = NVIC_PriorityGroup;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the NVIC peripheral according to the specified parameters in
|
||||||
|
* the NVIC_InitStruct.
|
||||||
|
*
|
||||||
|
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
|
||||||
|
* configuration information for the specified NVIC peripheral.
|
||||||
|
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range is 0.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 7.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 3.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 3.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 1.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 7.
|
||||||
|
* NVIC_IRQChannelSubPriority - range range is 0.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
|
||||||
|
{
|
||||||
|
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
|
||||||
|
if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
|
||||||
|
{
|
||||||
|
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
|
||||||
|
}
|
||||||
|
#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_2Level)
|
||||||
|
if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
|
||||||
|
{
|
||||||
|
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 2)
|
||||||
|
{
|
||||||
|
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_4Level)
|
||||||
|
if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
|
||||||
|
{
|
||||||
|
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 4)
|
||||||
|
{
|
||||||
|
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 6) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_8Level)
|
||||||
|
if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
|
||||||
|
{
|
||||||
|
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 8)
|
||||||
|
{
|
||||||
|
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 5) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||||
|
{
|
||||||
|
NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,86 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_opa.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the OPA firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_opa.h"
|
||||||
|
|
||||||
|
#define OPA_MASK ((uint32_t)0x000F)
|
||||||
|
#define OPA_Total_NUM 4
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn OPA_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the OPA peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void OPA_DeInit(void)
|
||||||
|
{
|
||||||
|
OPA->CR = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn OPA_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the OPA peripheral according to the specified
|
||||||
|
* parameters in the OPA_InitStruct.
|
||||||
|
*
|
||||||
|
* @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0;
|
||||||
|
tmp = OPA->CR;
|
||||||
|
tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
|
||||||
|
tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
|
||||||
|
OPA->CR = tmp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn OPA_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each OPA_StructInit member with its reset value.
|
||||||
|
*
|
||||||
|
* @param OPA_StructInit - pointer to a OPA_InitTypeDef structure
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
|
||||||
|
{
|
||||||
|
OPA_InitStruct->Mode = OUT_IO_OUT1;
|
||||||
|
OPA_InitStruct->PSEL = CHP0;
|
||||||
|
OPA_InitStruct->NSEL = CHN0;
|
||||||
|
OPA_InitStruct->OPA_NUM = OPA1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn OPA_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified OPA peripheral.
|
||||||
|
*
|
||||||
|
* @param OPA_NUM - Select OPA
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState == ENABLE)
|
||||||
|
{
|
||||||
|
OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM));
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,361 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_pwr.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the PWR firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_pwr.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* PWR registers bit mask */
|
||||||
|
/* CTLR register bit mask */
|
||||||
|
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC)
|
||||||
|
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the PWR peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_BackupAccessCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables access to the RTC and backup registers.
|
||||||
|
*
|
||||||
|
* @param NewState - new state of the access to the RTC and backup registers,
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_BackupAccessCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
PWR->CTLR |= (1 << 8);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
PWR->CTLR &= ~(1 << 8);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_PVDCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||||
|
*
|
||||||
|
* @param NewState - new state of the PVD(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_PVDCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
PWR->CTLR |= (1 << 4);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
PWR->CTLR &= ~(1 << 4);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_PVDLevelConfig
|
||||||
|
*
|
||||||
|
* @brief Configures the voltage threshold detected by the Power Voltage
|
||||||
|
* Detector(PVD).
|
||||||
|
*
|
||||||
|
* @param PWR_PVDLevel - specifies the PVD detection level
|
||||||
|
* PWR_PVDLevel_MODE0 - PVD detection level set to mode 0.
|
||||||
|
* PWR_PVDLevel_MODE1 - PVD detection level set to mode 1.
|
||||||
|
* PWR_PVDLevel_MODE2 - PVD detection level set to mode 2.
|
||||||
|
* PWR_PVDLevel_MODE3 - PVD detection level set to mode 3.
|
||||||
|
* PWR_PVDLevel_MODE4 - PVD detection level set to mode 4.
|
||||||
|
* PWR_PVDLevel_MODE5 - PVD detection level set to mode 5.
|
||||||
|
* PWR_PVDLevel_MODE6 - PVD detection level set to mode 6.
|
||||||
|
* PWR_PVDLevel_MODE7 - PVD detection level set to mode 7.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
tmpreg &= CTLR_PLS_MASK;
|
||||||
|
tmpreg |= PWR_PVDLevel;
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_WakeUpPinCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the WakeUp Pin functionality.
|
||||||
|
*
|
||||||
|
* @param NewState - new state of the WakeUp Pin functionality
|
||||||
|
* (ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_WakeUpPinCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
PWR->CSR |= (1 << 8);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
PWR->CSR &= ~(1 << 8);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTOPMode
|
||||||
|
*
|
||||||
|
* @brief Enters STOP mode.
|
||||||
|
*
|
||||||
|
* @param PWR_Regulator - specifies the regulator state in STOP mode.
|
||||||
|
* PWR_Regulator_ON - STOP mode with regulator ON
|
||||||
|
* PWR_Regulator_LowPower - STOP mode with regulator in low power mode
|
||||||
|
* PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
|
||||||
|
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
|
||||||
|
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
tmpreg &= CTLR_DS_MASK;
|
||||||
|
tmpreg |= PWR_Regulator;
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||||
|
{
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
__WFE();
|
||||||
|
}
|
||||||
|
|
||||||
|
NVIC->SCTLR &= ~(1 << 2);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTANDBYMode
|
||||||
|
*
|
||||||
|
* @brief Enters STANDBY mode.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode(void)
|
||||||
|
{
|
||||||
|
PWR->CTLR |= PWR_CTLR_CWUF;
|
||||||
|
PWR->CTLR |= PWR_CTLR_PDDS;
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified PWR flag is set or not.
|
||||||
|
*
|
||||||
|
* @param PWR_FLAG - specifies the flag to check.
|
||||||
|
* PWR_FLAG_WU - Wake Up flag
|
||||||
|
* PWR_FLAG_SB - StandBy flag
|
||||||
|
* PWR_FLAG_PVDO - PVD Output
|
||||||
|
*
|
||||||
|
* @return The new state of PWR_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the PWR's pending flags.
|
||||||
|
*
|
||||||
|
* @param PWR_FLAG - specifies the flag to clear.
|
||||||
|
* PWR_FLAG_WU - Wake Up flag
|
||||||
|
* PWR_FLAG_SB - StandBy flag
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||||
|
{
|
||||||
|
PWR->CTLR |= PWR_FLAG << 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTANDBYMode_RAM
|
||||||
|
*
|
||||||
|
* @brief Enters STANDBY mode with RAM data retention function on.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode_RAM(void)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
|
||||||
|
tmpreg |= PWR_CTLR_CWUF;
|
||||||
|
tmpreg |= PWR_CTLR_PDDS;
|
||||||
|
|
||||||
|
//2K+30K in standby w power.
|
||||||
|
tmpreg |= (0x1 << 16) | (0x1 << 17);
|
||||||
|
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTANDBYMode_RAM_LV
|
||||||
|
*
|
||||||
|
* @brief Enters STANDBY mode with RAM data retention function and LV mode on.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_LV(void)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
|
||||||
|
tmpreg |= PWR_CTLR_CWUF;
|
||||||
|
tmpreg |= PWR_CTLR_PDDS;
|
||||||
|
|
||||||
|
//2K+30K in standby power.
|
||||||
|
tmpreg |= (0x1 << 16) | (0x1 << 17);
|
||||||
|
//2K+30K in standby LV .
|
||||||
|
tmpreg |= (0x1 << 20);
|
||||||
|
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN
|
||||||
|
*
|
||||||
|
* @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
|
||||||
|
tmpreg |= PWR_CTLR_CWUF;
|
||||||
|
tmpreg |= PWR_CTLR_PDDS;
|
||||||
|
|
||||||
|
//2K+30K in standby power (VBAT Enable).
|
||||||
|
tmpreg |= (0x1 << 18) | (0x1 << 19);
|
||||||
|
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN
|
||||||
|
*
|
||||||
|
* @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
|
||||||
|
tmpreg |= PWR_CTLR_CWUF;
|
||||||
|
tmpreg |= PWR_CTLR_PDDS;
|
||||||
|
|
||||||
|
//2K+30K in standby power (VBAT Enable).
|
||||||
|
tmpreg |= (0x1 << 18) | (0x1 << 19);
|
||||||
|
//2K+30K in standby LV .
|
||||||
|
tmpreg |= (0x1 << 20);
|
||||||
|
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTOPMode_RAM_LV
|
||||||
|
*
|
||||||
|
* @brief Enters STOP mode with RAM data retention function and LV mode on.
|
||||||
|
*
|
||||||
|
* @param PWR_Regulator - specifies the regulator state in STOP mode.
|
||||||
|
* PWR_Regulator_LowPower - STOP mode with regulator in low power mode
|
||||||
|
* PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
|
||||||
|
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
|
||||||
|
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
tmpreg &= CTLR_DS_MASK;
|
||||||
|
tmpreg |= PWR_Regulator;
|
||||||
|
|
||||||
|
tmpreg |= (0x1 << 20);
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||||
|
{
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
__WFE();
|
||||||
|
}
|
||||||
|
|
||||||
|
NVIC->SCTLR &= ~(1 << 2);
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,154 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_rng.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the RNG firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_rng.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the RNG peripheral.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RNG_Cmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
RNG->CR |= RNG_CR_RNGEN;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RNG->CR &= ~RNG_CR_RNGEN;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_GetRandomNumber
|
||||||
|
*
|
||||||
|
* @brief Returns a 32-bit random number.
|
||||||
|
*
|
||||||
|
* @return 32-bit random number.
|
||||||
|
*/
|
||||||
|
uint32_t RNG_GetRandomNumber(void)
|
||||||
|
{
|
||||||
|
return RNG->DR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the RNG interrupt.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return 32-bit random number.
|
||||||
|
*/
|
||||||
|
void RNG_ITConfig(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
RNG->CR |= RNG_CR_IE;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RNG->CR &= ~RNG_CR_IE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified RNG flag is set or not.
|
||||||
|
*
|
||||||
|
* @param RNG_FLAG - specifies the RNG flag to check.
|
||||||
|
* RNG_FLAG_DRDY - Data Ready flag.
|
||||||
|
* RNG_FLAG_CECS - Clock Error Current flag.
|
||||||
|
* RNG_FLAG_SECS - Seed Error Current flag.
|
||||||
|
*
|
||||||
|
* @return 32-bit random number.
|
||||||
|
*/
|
||||||
|
FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the RNG flags.
|
||||||
|
*
|
||||||
|
* @param RNG_FLAG - specifies the flag to clear.
|
||||||
|
* RNG_FLAG_CECS - Clock Error Current flag.
|
||||||
|
* RNG_FLAG_SECS - Seed Error Current flag.
|
||||||
|
*
|
||||||
|
* @return 32-bit random number.
|
||||||
|
*/
|
||||||
|
void RNG_ClearFlag(uint8_t RNG_FLAG)
|
||||||
|
{
|
||||||
|
RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified RNG interrupt has occurred or not.
|
||||||
|
*
|
||||||
|
* @param RNG_IT - specifies the RNG interrupt source to check.
|
||||||
|
* RNG_IT_CEI - Clock Error Interrupt.
|
||||||
|
* RNG_IT_SEI - Seed Error Interrupt.
|
||||||
|
*
|
||||||
|
* @return bitstatus:SET or RESET.
|
||||||
|
*/
|
||||||
|
ITStatus RNG_GetITStatus(uint8_t RNG_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((RNG->SR & RNG_IT) != (uint8_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the RNG interrupt pending bit(s).
|
||||||
|
*
|
||||||
|
* @param RNG_IT - specifies the RNG interrupt pending bit(s) to clear.
|
||||||
|
* RNG_IT_CEI - Clock Error Interrupt.
|
||||||
|
* RNG_IT_SEI - Seed Error Interrupt.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void RNG_ClearITPendingBit(uint8_t RNG_IT)
|
||||||
|
{
|
||||||
|
RNG->SR = (uint8_t)~RNG_IT;
|
||||||
|
}
|
||||||
@@ -0,0 +1,315 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_rtc.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the RTC firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_rtc.h"
|
||||||
|
|
||||||
|
/* RTC_Private_Defines */
|
||||||
|
#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */
|
||||||
|
#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified RTC interrupts.
|
||||||
|
*
|
||||||
|
* @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled.
|
||||||
|
* RTC_IT_OW - Overflow interrupt
|
||||||
|
* RTC_IT_ALR - Alarm interrupt
|
||||||
|
* RTC_IT_SEC - Second interrupt
|
||||||
|
*
|
||||||
|
* @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE).
|
||||||
|
*/
|
||||||
|
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
RTC->CTLRH |= RTC_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RTC->CTLRH &= (uint16_t)~RTC_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_EnterConfigMode
|
||||||
|
*
|
||||||
|
* @brief Enters the RTC configuration mode.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_EnterConfigMode(void)
|
||||||
|
{
|
||||||
|
RTC->CTLRL |= RTC_CTLRL_CNF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_ExitConfigMode
|
||||||
|
*
|
||||||
|
* @brief Exits from the RTC configuration mode.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_ExitConfigMode(void)
|
||||||
|
{
|
||||||
|
RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_GetCounter
|
||||||
|
*
|
||||||
|
* @brief Gets the RTC counter value
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
uint32_t RTC_GetCounter(void)
|
||||||
|
{
|
||||||
|
uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0;
|
||||||
|
uint16_t low1 = 0, low2 = 0;
|
||||||
|
|
||||||
|
do{
|
||||||
|
high1a = RTC->CNTH;
|
||||||
|
high1b = RTC->CNTH;
|
||||||
|
}while( high1a != high1b );
|
||||||
|
|
||||||
|
do{
|
||||||
|
low1 = RTC->CNTL;
|
||||||
|
low2 = RTC->CNTL;
|
||||||
|
}while( low1 != low2 );
|
||||||
|
|
||||||
|
do{
|
||||||
|
high2a = RTC->CNTH;
|
||||||
|
high2b = RTC->CNTH;
|
||||||
|
}while( high2a != high2b );
|
||||||
|
|
||||||
|
if(high1b != high2b)
|
||||||
|
{
|
||||||
|
do{
|
||||||
|
low1 = RTC->CNTL;
|
||||||
|
low2 = RTC->CNTL;
|
||||||
|
}while( low1 != low2 );
|
||||||
|
}
|
||||||
|
|
||||||
|
return (((uint32_t)high2b << 16) | low2);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_SetCounter
|
||||||
|
*
|
||||||
|
* @brief Sets the RTC counter value.
|
||||||
|
*
|
||||||
|
* @param CounterValue - RTC counter new value.
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void RTC_SetCounter(uint32_t CounterValue)
|
||||||
|
{
|
||||||
|
RTC_EnterConfigMode();
|
||||||
|
RTC->CNTH = CounterValue >> 16;
|
||||||
|
RTC->CNTL = (CounterValue & RTC_LSB_MASK);
|
||||||
|
RTC_ExitConfigMode();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_SetPrescaler
|
||||||
|
*
|
||||||
|
* @brief Sets the RTC prescaler value
|
||||||
|
*
|
||||||
|
* @param PrescalerValue - RTC prescaler new value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_SetPrescaler(uint32_t PrescalerValue)
|
||||||
|
{
|
||||||
|
RTC_EnterConfigMode();
|
||||||
|
RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
|
||||||
|
RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK);
|
||||||
|
RTC_ExitConfigMode();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_SetAlarm
|
||||||
|
*
|
||||||
|
* @brief Sets the RTC alarm value
|
||||||
|
*
|
||||||
|
* @param AlarmValue - RTC alarm new value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_SetAlarm(uint32_t AlarmValue)
|
||||||
|
{
|
||||||
|
RTC_EnterConfigMode();
|
||||||
|
RTC->ALRMH = AlarmValue >> 16;
|
||||||
|
RTC->ALRML = (AlarmValue & RTC_LSB_MASK);
|
||||||
|
RTC_ExitConfigMode();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_GetDivider
|
||||||
|
*
|
||||||
|
* @brief Gets the RTC divider value
|
||||||
|
*
|
||||||
|
* @return RTC Divider value
|
||||||
|
*/
|
||||||
|
uint32_t RTC_GetDivider(void)
|
||||||
|
{
|
||||||
|
uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0;
|
||||||
|
uint16_t low1 = 0, low2 = 0;
|
||||||
|
|
||||||
|
do{
|
||||||
|
high1a = RTC->DIVH;
|
||||||
|
high1b = RTC->DIVH;
|
||||||
|
}while( high1a != high1b );
|
||||||
|
|
||||||
|
do{
|
||||||
|
low1 = RTC->DIVL;
|
||||||
|
low2 = RTC->DIVL;
|
||||||
|
}while( low1 != low2 );
|
||||||
|
|
||||||
|
do{
|
||||||
|
high2a = RTC->DIVH;
|
||||||
|
high2b = RTC->DIVH;
|
||||||
|
}while( high2a != high2b );
|
||||||
|
|
||||||
|
if(high1b != high2b)
|
||||||
|
{
|
||||||
|
do{
|
||||||
|
low1 = RTC->DIVL;
|
||||||
|
low2 = RTC->DIVL;
|
||||||
|
}while( low1 != low2 );
|
||||||
|
}
|
||||||
|
|
||||||
|
return ((((uint32_t)high2b & (uint32_t)0x000F) << 16) | low2);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_WaitForLastTask
|
||||||
|
*
|
||||||
|
* @brief Waits until last write operation on RTC registers has finished
|
||||||
|
* Note-
|
||||||
|
* This function must be called before any write to RTC registers.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_WaitForLastTask(void)
|
||||||
|
{
|
||||||
|
while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_WaitForSynchro
|
||||||
|
*
|
||||||
|
* @brief Waits until the RTC registers are synchronized with RTC APB clock
|
||||||
|
* Note-
|
||||||
|
* This function must be called before any read operation after an APB reset
|
||||||
|
* or an APB clock stop.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_WaitForSynchro(void)
|
||||||
|
{
|
||||||
|
RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF;
|
||||||
|
while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified RTC flag is set or not
|
||||||
|
*
|
||||||
|
* @param RTC_FLAG- specifies the flag to check
|
||||||
|
* RTC_FLAG_RTOFF - RTC Operation OFF flag
|
||||||
|
* RTC_FLAG_RSF - Registers Synchronized flag
|
||||||
|
* RTC_FLAG_OW - Overflow flag
|
||||||
|
* RTC_FLAG_ALR - Alarm flag
|
||||||
|
* RTC_FLAG_SEC - Second flag
|
||||||
|
*
|
||||||
|
* @return The new state of RTC_FLAG (SET or RESET)
|
||||||
|
*/
|
||||||
|
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the RTC's pending flags
|
||||||
|
*
|
||||||
|
* @param RTC_FLAG - specifies the flag to clear
|
||||||
|
* RTC_FLAG_RSF - Registers Synchronized flag
|
||||||
|
* RTC_FLAG_OW - Overflow flag
|
||||||
|
* RTC_FLAG_ALR - Alarm flag
|
||||||
|
* RTC_FLAG_SEC - Second flag
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_ClearFlag(uint16_t RTC_FLAG)
|
||||||
|
{
|
||||||
|
RTC->CTLRL &= (uint16_t)~RTC_FLAG;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified RTC interrupt has occurred or not
|
||||||
|
*
|
||||||
|
* @param RTC_IT - specifies the RTC interrupts sources to check
|
||||||
|
* RTC_FLAG_OW - Overflow interrupt
|
||||||
|
* RTC_FLAG_ALR - Alarm interrupt
|
||||||
|
* RTC_FLAG_SEC - Second interrupt
|
||||||
|
*
|
||||||
|
* @return The new state of the RTC_IT (SET or RESET)
|
||||||
|
*/
|
||||||
|
ITStatus RTC_GetITStatus(uint16_t RTC_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT);
|
||||||
|
if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the RTC's interrupt pending bits
|
||||||
|
*
|
||||||
|
* @param RTC_IT - specifies the interrupt pending bit to clear
|
||||||
|
* RTC_FLAG_OW - Overflow interrupt
|
||||||
|
* RTC_FLAG_ALR - Alarm interrupt
|
||||||
|
* RTC_FLAG_SEC - Second interrupt
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_ClearITPendingBit(uint16_t RTC_IT)
|
||||||
|
{
|
||||||
|
RTC->CTLRL &= (uint16_t)~RTC_IT;
|
||||||
|
}
|
||||||
@@ -0,0 +1,672 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_SDIO.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the SDIO firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_sdio.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
|
||||||
|
|
||||||
|
/* CLKCR register clear mask */
|
||||||
|
#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
|
||||||
|
|
||||||
|
/* SDIO PWRCTRL Mask */
|
||||||
|
#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
|
||||||
|
|
||||||
|
/* SDIO DCTRL Clear Mask */
|
||||||
|
#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
|
||||||
|
|
||||||
|
/* CMD Register clear mask */
|
||||||
|
#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
|
||||||
|
|
||||||
|
/* SDIO RESP Registers Address */
|
||||||
|
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the SDIO peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void SDIO_DeInit(void)
|
||||||
|
{
|
||||||
|
SDIO->POWER = 0x00000000;
|
||||||
|
SDIO->CLKCR = 0x00000000;
|
||||||
|
SDIO->ARG = 0x00000000;
|
||||||
|
SDIO->CMD = 0x00000000;
|
||||||
|
SDIO->DTIMER = 0x00000000;
|
||||||
|
SDIO->DLEN = 0x00000000;
|
||||||
|
SDIO->DCTRL = 0x00000000;
|
||||||
|
SDIO->ICR = 0x00C007FF;
|
||||||
|
SDIO->MASK = 0x00000000;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the SDIO peripheral according to the specified
|
||||||
|
* parameters in the SDIO_InitStruct.
|
||||||
|
*
|
||||||
|
* @param SDIO_InitStruct - pointer to a SDIO_InitTypeDef structure
|
||||||
|
* that contains the configuration information for the SDIO peripheral.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = SDIO->CLKCR;
|
||||||
|
tmpreg &= CLKCR_CLEAR_MASK;
|
||||||
|
tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
|
||||||
|
SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
|
||||||
|
SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
|
||||||
|
|
||||||
|
SDIO->CLKCR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each SDIO_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which
|
||||||
|
* will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct)
|
||||||
|
{
|
||||||
|
SDIO_InitStruct->SDIO_ClockDiv = 0x00;
|
||||||
|
SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
|
||||||
|
SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
|
||||||
|
SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
|
||||||
|
SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
|
||||||
|
SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_ClockCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SDIO Clock.
|
||||||
|
*
|
||||||
|
* @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which
|
||||||
|
* will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_ClockCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->CLKCR |= (1 << 8);
|
||||||
|
else
|
||||||
|
SDIO->CLKCR &= ~(1 << 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SetPowerState
|
||||||
|
*
|
||||||
|
* @brief Sets the power status of the controller.
|
||||||
|
*
|
||||||
|
* @param SDIO_PowerState - new state of the Power state.
|
||||||
|
* SDIO_PowerState_OFF
|
||||||
|
* SDIO_PowerState_ON
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
|
||||||
|
{
|
||||||
|
SDIO->POWER &= PWR_PWRCTRL_MASK;
|
||||||
|
SDIO->POWER |= SDIO_PowerState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetPowerState
|
||||||
|
*
|
||||||
|
* @brief Gets the power status of the controller.
|
||||||
|
*
|
||||||
|
* @param CounterValue - RTC counter new value.
|
||||||
|
*
|
||||||
|
* @return power state -
|
||||||
|
* 0x00 - Power OFF
|
||||||
|
* 0x02 - Power UP
|
||||||
|
* 0x03 - Power ON
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetPowerState(void)
|
||||||
|
{
|
||||||
|
return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SDIO interrupts.
|
||||||
|
*
|
||||||
|
* @param DIO_IT - specifies the SDIO interrupt sources to be enabled or disabled.
|
||||||
|
* SDIO_IT_CCRCFAIL
|
||||||
|
* SDIO_IT_DCRCFAIL
|
||||||
|
* SDIO_IT_CTIMEOUT
|
||||||
|
* SDIO_IT_DTIMEOUT
|
||||||
|
* SDIO_IT_TXUNDERR
|
||||||
|
* SDIO_IT_RXOVERR
|
||||||
|
* SDIO_IT_CMDREND
|
||||||
|
* SDIO_IT_CMDSENT
|
||||||
|
* SDIO_IT_DATAEND
|
||||||
|
* SDIO_IT_STBITERR
|
||||||
|
* SDIO_IT_DBCKEND
|
||||||
|
* SDIO_IT_CMDACT
|
||||||
|
* SDIO_IT_TXACT
|
||||||
|
* SDIO_IT_RXACT
|
||||||
|
* SDIO_IT_TXFIFOHE
|
||||||
|
* SDIO_IT_RXFIFOHF
|
||||||
|
* SDIO_IT_TXFIFOF
|
||||||
|
* SDIO_IT_RXFIFOF
|
||||||
|
* SDIO_IT_TXFIFOE
|
||||||
|
* SDIO_IT_RXFIFOE
|
||||||
|
* SDIO_IT_TXDAVL
|
||||||
|
* SDIO_IT_RXDAVL
|
||||||
|
* SDIO_IT_SDIOIT
|
||||||
|
* SDIO_IT_CEATAEND
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SDIO->MASK |= SDIO_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SDIO->MASK &= ~SDIO_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_DMACmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SDIO DMA request.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_DMACmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->DCTRL |= (1 << 3);
|
||||||
|
else
|
||||||
|
SDIO->DCTRL &= ~(1 << 3);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SendCommand
|
||||||
|
*
|
||||||
|
* @brief Initializes the SDIO Command according to the specified
|
||||||
|
* parameters in the SDIO_CmdInitStruct and send the command.
|
||||||
|
* @param SDIO_CmdInitStruct - pointer to a SDIO_CmdInitTypeDef
|
||||||
|
* structure that contains the configuration information for
|
||||||
|
* ddthe SDIO command.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
|
||||||
|
|
||||||
|
tmpreg = SDIO->CMD;
|
||||||
|
tmpreg &= CMD_CLEAR_MASK;
|
||||||
|
tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
|
||||||
|
|
||||||
|
SDIO->CMD = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_CmdStructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each SDIO_CmdInitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param SDIO_CmdInitStruct - pointer to an SDIO_CmdInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
|
||||||
|
{
|
||||||
|
SDIO_CmdInitStruct->SDIO_Argument = 0x00;
|
||||||
|
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
|
||||||
|
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
|
||||||
|
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
|
||||||
|
SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetCommandResponse
|
||||||
|
*
|
||||||
|
* @brief Returns command index of last command for which response received.
|
||||||
|
*
|
||||||
|
* @return Returns the command index of the last command response received.
|
||||||
|
*/
|
||||||
|
uint8_t SDIO_GetCommandResponse(void)
|
||||||
|
{
|
||||||
|
return (uint8_t)(SDIO->RESPCMD);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetResponse
|
||||||
|
*
|
||||||
|
* @brief Returns response received from the card for the last command.
|
||||||
|
*
|
||||||
|
* @param SDIO_RESP - Specifies the SDIO response register.
|
||||||
|
* SDIO_RESP1 - Response Register 1
|
||||||
|
* SDIO_RESP2 - Response Register 2
|
||||||
|
* SDIO_RESP3 - Response Register 3
|
||||||
|
* SDIO_RESP4 - Response Register 4
|
||||||
|
*
|
||||||
|
* @return Returns the command index of the last command response received.
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = SDIO_RESP_ADDR + SDIO_RESP;
|
||||||
|
|
||||||
|
return (*(__IO uint32_t *)tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_DataConfig
|
||||||
|
*
|
||||||
|
* @brief Initializes the SDIO data path according to the specified
|
||||||
|
*
|
||||||
|
* @param SDIO_DataInitStruct - pointer to a SDIO_DataInitTypeDef structure that
|
||||||
|
* contains the configuration information for the SDIO command.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
|
||||||
|
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
|
||||||
|
tmpreg = SDIO->DCTRL;
|
||||||
|
tmpreg &= DCTRL_CLEAR_MASK;
|
||||||
|
tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
|
||||||
|
|
||||||
|
SDIO->DCTRL = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_DataStructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each SDIO_DataInitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param SDIO_DataInitStruct - pointer to an SDIO_DataInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
|
||||||
|
{
|
||||||
|
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
|
||||||
|
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
|
||||||
|
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
|
||||||
|
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
|
||||||
|
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
|
||||||
|
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetDataCounter
|
||||||
|
*
|
||||||
|
* @brief Returns number of remaining data bytes to be transferred.
|
||||||
|
*
|
||||||
|
* @return Number of remaining data bytes to be transferred
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetDataCounter(void)
|
||||||
|
{
|
||||||
|
return SDIO->DCOUNT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_ReadData
|
||||||
|
*
|
||||||
|
* @brief Read one data word from Rx FIFO.
|
||||||
|
*
|
||||||
|
* @return Data received
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_ReadData(void)
|
||||||
|
{
|
||||||
|
return SDIO->FIFO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_WriteData
|
||||||
|
*
|
||||||
|
* @brief Write one data word to Tx FIFO.
|
||||||
|
*
|
||||||
|
* @param Data - 32-bit data word to write.
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void SDIO_WriteData(uint32_t Data)
|
||||||
|
{
|
||||||
|
SDIO->FIFO = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetFIFOCount
|
||||||
|
*
|
||||||
|
* @brief Returns the number of words left to be written to or read from FIFO.
|
||||||
|
*
|
||||||
|
* @return Remaining number of words.
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetFIFOCount(void)
|
||||||
|
{
|
||||||
|
return SDIO->FIFOCNT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_StartSDIOReadWait
|
||||||
|
*
|
||||||
|
* @brief Starts the SD I/O Read Wait operation.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_StartSDIOReadWait(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->DCTRL |= (1 << 8);
|
||||||
|
else
|
||||||
|
SDIO->DCTRL &= ~(1 << 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_StopSDIOReadWait
|
||||||
|
*
|
||||||
|
* @brief Stops the SD I/O Read Wait operation.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_StopSDIOReadWait(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->DCTRL |= (1 << 9);
|
||||||
|
else
|
||||||
|
SDIO->DCTRL &= ~(1 << 9);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SetSDIOReadWaitMode
|
||||||
|
*
|
||||||
|
* @brief Sets one of the two options of inserting read wait interval.
|
||||||
|
*
|
||||||
|
* @param SDIO_ReadWaitMode - SD I/O Read Wait operation mode.
|
||||||
|
* SDIO_ReadWaitMode_CLK - Read Wait control by stopping SDIOCLK
|
||||||
|
* SDIO_ReadWaitMode_DATA2 - Read Wait control using SDIO_DATA2
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
|
||||||
|
{
|
||||||
|
if(SDIO_ReadWaitMode)
|
||||||
|
SDIO->DCTRL |= (1 << 10);
|
||||||
|
else
|
||||||
|
SDIO->DCTRL &= ~(1 << 10);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SetSDIOOperation
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SD I/O Mode Operation.
|
||||||
|
*
|
||||||
|
* @param NewState: ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_SetSDIOOperation(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->DCTRL |= (1 << 11);
|
||||||
|
else
|
||||||
|
SDIO->DCTRL &= ~(1 << 11);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SendSDIOSuspendCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SD I/O Mode suspend command sending.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->CMD |= (1 << 11);
|
||||||
|
else
|
||||||
|
SDIO->CMD &= ~(1 << 11);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_CommandCompletionCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the command completion signal.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_CommandCompletionCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->CMD |= (1 << 12);
|
||||||
|
else
|
||||||
|
SDIO->CMD &= ~(1 << 12);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_CEATAITCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the CE-ATA interrupt.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_CEATAITCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->CMD |= (1 << 13);
|
||||||
|
else
|
||||||
|
SDIO->CMD &= ~(1 << 13);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SendCEATACmd
|
||||||
|
*
|
||||||
|
* @brief Sends CE-ATA command (CMD61).
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void SDIO_SendCEATACmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->CMD |= (1 << 14);
|
||||||
|
else
|
||||||
|
SDIO->CMD &= ~(1 << 14);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified SDIO flag is set or not.
|
||||||
|
*
|
||||||
|
* @param SDIO_FLAG - specifies the flag to check.
|
||||||
|
* SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed)
|
||||||
|
* SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed)
|
||||||
|
* SDIO_FLAG_CTIMEOUT - Command response timeout
|
||||||
|
* SDIO_FLAG_DTIMEOUT - Data timeout
|
||||||
|
* SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error
|
||||||
|
* SDIO_FLAG_RXOVERR - Received FIFO overrun error
|
||||||
|
* SDIO_FLAG_CMDREND - Command response received (CRC check passed)
|
||||||
|
* SDIO_FLAG_CMDSENT - Command sent (no response required)
|
||||||
|
* SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero)
|
||||||
|
* SDIO_FLAG_STBITERR - Start bit not detected on all data signals
|
||||||
|
* in wide bus mode.
|
||||||
|
* SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed)
|
||||||
|
* SDIO_FLAG_CMDACT - Command transfer in progress
|
||||||
|
* SDIO_FLAG_TXACT - Data transmit in progress
|
||||||
|
* SDIO_FLAG_RXACT - Data receive in progress
|
||||||
|
* SDIO_FLAG_TXFIFOHE - Transmit FIFO Half Empty
|
||||||
|
* SDIO_FLAG_RXFIFOHF - Receive FIFO Half Full
|
||||||
|
* SDIO_FLAG_TXFIFOF - Transmit FIFO full
|
||||||
|
* SDIO_FLAG_RXFIFOF - Receive FIFO full
|
||||||
|
* SDIO_FLAG_TXFIFOE - Transmit FIFO empty
|
||||||
|
* SDIO_FLAG_RXFIFOE - Receive FIFO empty
|
||||||
|
* SDIO_FLAG_TXDAVL - Data available in transmit FIFO
|
||||||
|
* SDIO_FLAG_RXDAVL - Data available in receive FIFO
|
||||||
|
* SDIO_FLAG_SDIOIT - SD I/O interrupt received
|
||||||
|
* SDIO_FLAG_CEATAEND - CE-ATA command completion signal received
|
||||||
|
* for CMD61
|
||||||
|
*
|
||||||
|
* @return ITStatus - SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the SDIO's pending flags.
|
||||||
|
*
|
||||||
|
* @param SDIO_FLAG - specifies the flag to clear.
|
||||||
|
* SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed)
|
||||||
|
* SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed)
|
||||||
|
* SDIO_FLAG_CTIMEOUT - Command response timeout
|
||||||
|
* SDIO_FLAG_DTIMEOUT - Data timeout
|
||||||
|
* SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error
|
||||||
|
* SDIO_FLAG_RXOVERR - Received FIFO overrun error
|
||||||
|
* SDIO_FLAG_CMDREND - Command response received (CRC check passed)
|
||||||
|
* SDIO_FLAG_CMDSENT - Command sent (no response required)
|
||||||
|
* SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero)
|
||||||
|
* SDIO_FLAG_STBITERR - Start bit not detected on all data signals
|
||||||
|
* in wide bus mode
|
||||||
|
* SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed)
|
||||||
|
* SDIO_FLAG_SDIOIT - SD I/O interrupt received
|
||||||
|
* SDIO_FLAG_CEATAEND - CE-ATA command completion signal received for CMD61
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
|
||||||
|
{
|
||||||
|
SDIO->ICR = SDIO_FLAG;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified SDIO interrupt has occurred or not.
|
||||||
|
*
|
||||||
|
* @param SDIO_IT: specifies the SDIO interrupt source to check.
|
||||||
|
* SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt
|
||||||
|
* SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt
|
||||||
|
* SDIO_IT_CTIMEOUT - Command response timeout interrupt
|
||||||
|
* SDIO_IT_DTIMEOUT - Data timeout interrupt
|
||||||
|
* SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt
|
||||||
|
* SDIO_IT_RXOVERR - Received FIFO overrun error interrupt
|
||||||
|
* SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt
|
||||||
|
* SDIO_IT_CMDSENT - Command sent (no response required) interrupt
|
||||||
|
* SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* SDIO_IT_STBITERR - Start bit not detected on all data signals in wide
|
||||||
|
* bus mode interrupt
|
||||||
|
* SDIO_IT_DBCKEND - Data block sent/received (CRC check passed) interrupt
|
||||||
|
* SDIO_IT_CMDACT - Command transfer in progress interrupt
|
||||||
|
* SDIO_IT_TXACT - Data transmit in progress interrupt
|
||||||
|
* SDIO_IT_RXACT - Data receive in progress interrupt
|
||||||
|
* SDIO_IT_TXFIFOHE - Transmit FIFO Half Empty interrupt
|
||||||
|
* SDIO_IT_RXFIFOHF - Receive FIFO Half Full interrupt
|
||||||
|
* SDIO_IT_TXFIFOF - Transmit FIFO full interrupt
|
||||||
|
* SDIO_IT_RXFIFOF - Receive FIFO full interrupt
|
||||||
|
* SDIO_IT_TXFIFOE - Transmit FIFO empty interrupt
|
||||||
|
* SDIO_IT_RXFIFOE - Receive FIFO empty interrupt
|
||||||
|
* SDIO_IT_TXDAVL - Data available in transmit FIFO interrupt
|
||||||
|
* SDIO_IT_RXDAVL - Data available in receive FIFO interrupt
|
||||||
|
* SDIO_IT_SDIOIT - SD I/O interrupt received interrupt
|
||||||
|
* SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 interrupt
|
||||||
|
*
|
||||||
|
* @return ITStatus:SET or RESET
|
||||||
|
*/
|
||||||
|
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the SDIO's interrupt pending bits.
|
||||||
|
*
|
||||||
|
* @param SDIO_IT - specifies the interrupt pending bit to clear.
|
||||||
|
* SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt
|
||||||
|
* SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt
|
||||||
|
* SDIO_IT_CTIMEOUT - Command response timeout interrupt
|
||||||
|
* SDIO_IT_DTIMEOUT - Data timeout interrupt
|
||||||
|
* SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt
|
||||||
|
* SDIO_IT_RXOVERR - Received FIFO overrun error interrupt
|
||||||
|
* SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt
|
||||||
|
* SDIO_IT_CMDSENT - Command sent (no response required) interrupt
|
||||||
|
* SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* SDIO_IT_STBITERR - Start bit not detected on all data signals in wide
|
||||||
|
* bus mode interrupt
|
||||||
|
* SDIO_IT_SDIOIT - SD I/O interrupt received interrupt
|
||||||
|
* SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
|
||||||
|
{
|
||||||
|
SDIO->ICR = SDIO_IT;
|
||||||
|
}
|
||||||
@@ -0,0 +1,668 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_spi.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the SPI firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_spi.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* SPI SPE mask */
|
||||||
|
#define CTLR1_SPE_Set ((uint16_t)0x0040)
|
||||||
|
#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
|
||||||
|
|
||||||
|
/* I2S I2SE mask */
|
||||||
|
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
|
||||||
|
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
|
||||||
|
|
||||||
|
/* SPI CRCNext mask */
|
||||||
|
#define CTLR1_CRCNext_Set ((uint16_t)0x1000)
|
||||||
|
|
||||||
|
/* SPI CRCEN mask */
|
||||||
|
#define CTLR1_CRCEN_Set ((uint16_t)0x2000)
|
||||||
|
#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF)
|
||||||
|
|
||||||
|
/* SPI SSOE mask */
|
||||||
|
#define CTLR2_SSOE_Set ((uint16_t)0x0004)
|
||||||
|
#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB)
|
||||||
|
|
||||||
|
/* SPI registers Masks */
|
||||||
|
#define CTLR1_CLEAR_Mask ((uint16_t)0x3040)
|
||||||
|
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
|
||||||
|
|
||||||
|
/* SPI or I2S mode selection masks */
|
||||||
|
#define SPI_Mode_Select ((uint16_t)0xF7FF)
|
||||||
|
#define I2S_Mode_Select ((uint16_t)0x0800)
|
||||||
|
|
||||||
|
/* I2S clock source selection masks */
|
||||||
|
#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
|
||||||
|
#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
|
||||||
|
#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
|
||||||
|
#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the SPIx peripheral registers to their default
|
||||||
|
* reset values (Affects also the I2Ss).
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
|
||||||
|
{
|
||||||
|
if(SPIx == SPI1)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
|
||||||
|
}
|
||||||
|
else if(SPIx == SPI2)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(SPIx == SPI3)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the SPIx peripheral according to the specified
|
||||||
|
* parameters in the SPI_InitStruct.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified SPI peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = SPIx->CTLR1;
|
||||||
|
tmpreg &= CTLR1_CLEAR_Mask;
|
||||||
|
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
|
||||||
|
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
|
||||||
|
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
|
||||||
|
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
|
||||||
|
|
||||||
|
SPIx->CTLR1 = tmpreg;
|
||||||
|
SPIx->I2SCFGR &= SPI_Mode_Select;
|
||||||
|
SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn I2S_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the SPIx peripheral according to the specified
|
||||||
|
* parameters in the I2S_InitStruct.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* (configured in I2S mode).
|
||||||
|
* I2S_InitStruct - pointer to an I2S_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified SPI peripheral
|
||||||
|
* configured in I2S mode.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
|
||||||
|
uint32_t tmp = 0;
|
||||||
|
RCC_ClocksTypeDef RCC_Clocks;
|
||||||
|
uint32_t sourceclock = 0;
|
||||||
|
|
||||||
|
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
|
||||||
|
SPIx->I2SPR = 0x0002;
|
||||||
|
tmpreg = SPIx->I2SCFGR;
|
||||||
|
|
||||||
|
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
|
||||||
|
{
|
||||||
|
i2sodd = (uint16_t)0;
|
||||||
|
i2sdiv = (uint16_t)2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
|
||||||
|
{
|
||||||
|
packetlength = 1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
packetlength = 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(((uint32_t)SPIx) == SPI2_BASE)
|
||||||
|
{
|
||||||
|
tmp = I2S2_CLOCK_SRC;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp = I2S3_CLOCK_SRC;
|
||||||
|
}
|
||||||
|
|
||||||
|
RCC_GetClocksFreq(&RCC_Clocks);
|
||||||
|
|
||||||
|
sourceclock = RCC_Clocks.SYSCLK_Frequency;
|
||||||
|
|
||||||
|
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
|
||||||
|
{
|
||||||
|
tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||||
|
}
|
||||||
|
|
||||||
|
tmp = tmp / 10;
|
||||||
|
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
|
||||||
|
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
|
||||||
|
i2sodd = (uint16_t)(i2sodd << 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
if((i2sdiv < 2) || (i2sdiv > 0xFF))
|
||||||
|
{
|
||||||
|
i2sdiv = 2;
|
||||||
|
i2sodd = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
|
||||||
|
tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode |
|
||||||
|
(uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat |
|
||||||
|
(uint16_t)I2S_InitStruct->I2S_CPOL))));
|
||||||
|
SPIx->I2SCFGR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each SPI_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which
|
||||||
|
* will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
|
||||||
|
{
|
||||||
|
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||||
|
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
|
||||||
|
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
|
||||||
|
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
|
||||||
|
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
|
||||||
|
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||||
|
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
|
||||||
|
SPI_InitStruct->SPI_CRCPolynomial = 7;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn I2S_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each I2S_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which
|
||||||
|
* will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
|
||||||
|
{
|
||||||
|
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
|
||||||
|
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
|
||||||
|
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
|
||||||
|
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
|
||||||
|
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
|
||||||
|
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified SPI peripheral.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 |= CTLR1_SPE_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 &= CTLR1_SPE_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn I2S_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified SPI/I2S interrupts.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to be
|
||||||
|
* enabled or disabled.
|
||||||
|
* SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
|
||||||
|
* SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask.
|
||||||
|
* SPI_I2S_IT_ERR - Error interrupt mask.
|
||||||
|
* NewState: ENABLE or DISABLE.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
uint16_t itpos = 0, itmask = 0;
|
||||||
|
|
||||||
|
itpos = SPI_I2S_IT >> 4;
|
||||||
|
itmask = (uint16_t)1 << (uint16_t)itpos;
|
||||||
|
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 |= itmask;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 &= (uint16_t)~itmask;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_DMACmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SPIx/I2Sx DMA interface.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to
|
||||||
|
* be enabled or disabled.
|
||||||
|
* SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
|
||||||
|
* SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 |= SPI_I2S_DMAReq;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_SendData
|
||||||
|
*
|
||||||
|
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* Data - Data to be transmitted.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
|
||||||
|
{
|
||||||
|
SPIx->DATAR = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_ReceiveData
|
||||||
|
*
|
||||||
|
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* Data - Data to be transmitted.
|
||||||
|
*
|
||||||
|
* @return SPIx->DATAR - The value of the received data.
|
||||||
|
*/
|
||||||
|
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
|
||||||
|
{
|
||||||
|
return SPIx->DATAR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_NSSInternalSoftwareConfig
|
||||||
|
*
|
||||||
|
* @brief Configures internally by software the NSS pin for the selected SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* SPI_NSSInternalSoft -
|
||||||
|
* SPI_NSSInternalSoft_Set - Set NSS pin internally.
|
||||||
|
* SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
|
||||||
|
{
|
||||||
|
if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_SSOutputCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SS output for the selected SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* NewState - new state of the SPIx SS output.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 |= CTLR2_SSOE_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 &= CTLR2_SSOE_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_DataSizeConfig
|
||||||
|
*
|
||||||
|
* @brief Configures the data size for the selected SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* SPI_DataSize - specifies the SPI data size.
|
||||||
|
* SPI_DataSize_16b - Set data frame format to 16bit.
|
||||||
|
* SPI_DataSize_8b - Set data frame format to 8bit.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b;
|
||||||
|
SPIx->CTLR1 |= SPI_DataSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_TransmitCRC
|
||||||
|
*
|
||||||
|
* @brief Transmit the SPIx CRC value.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_TransmitCRC(SPI_TypeDef *SPIx)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 |= CTLR1_CRCNext_Set;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_CalculateCRC
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the CRC value calculation of the transferred bytes.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* NewState - new state of the SPIx CRC value calculation.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 |= CTLR1_CRCEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_GetCRC
|
||||||
|
*
|
||||||
|
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* SPI_CRC - specifies the CRC register to be read.
|
||||||
|
* SPI_CRC_Tx - Selects Tx CRC register.
|
||||||
|
* SPI_CRC_Rx - Selects Rx CRC register.
|
||||||
|
*
|
||||||
|
* @return crcreg: The selected CRC register value.
|
||||||
|
*/
|
||||||
|
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
|
||||||
|
{
|
||||||
|
uint16_t crcreg = 0;
|
||||||
|
|
||||||
|
if(SPI_CRC != SPI_CRC_Rx)
|
||||||
|
{
|
||||||
|
crcreg = SPIx->TCRCR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
crcreg = SPIx->RCRCR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return crcreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_GetCRCPolynomial
|
||||||
|
*
|
||||||
|
* @brief Returns the CRC Polynomial register value for the specified SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
*
|
||||||
|
* @return SPIx->CRCR - The CRC Polynomial register value.
|
||||||
|
*/
|
||||||
|
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
|
||||||
|
{
|
||||||
|
return SPIx->CRCR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_BiDirectionalLineConfig
|
||||||
|
*
|
||||||
|
* @brief Selects the data transfer direction in bi-directional mode
|
||||||
|
* for the specified SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* SPI_Direction - specifies the data transfer direction in
|
||||||
|
* bi-directional mode.
|
||||||
|
* SPI_Direction_Tx - Selects Tx transmission direction.
|
||||||
|
* SPI_Direction_Rx - Selects Rx receive direction.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
|
||||||
|
{
|
||||||
|
if(SPI_Direction == SPI_Direction_Tx)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 |= SPI_Direction_Tx;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 &= SPI_Direction_Rx;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified SPI/I2S flag is set or not.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
|
||||||
|
* SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
|
||||||
|
* SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
|
||||||
|
* SPI_I2S_FLAG_BSY - Busy flag.
|
||||||
|
* SPI_I2S_FLAG_OVR - Overrun flag.
|
||||||
|
* SPI_FLAG_MODF - Mode Fault flag.
|
||||||
|
* SPI_FLAG_CRCERR - CRC Error flag.
|
||||||
|
* I2S_FLAG_UDR - Underrun Error flag.
|
||||||
|
* I2S_FLAG_CHSIDE - Channel Side flag.
|
||||||
|
*
|
||||||
|
* @return FlagStatus: SET or RESET.
|
||||||
|
*/
|
||||||
|
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the SPIx CRC Error (CRCERR) flag.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* SPI_I2S_FLAG - specifies the SPI flag to clear.
|
||||||
|
* SPI_FLAG_CRCERR - CRC Error flag.
|
||||||
|
* Note-
|
||||||
|
* - OVR (OverRun error) flag is cleared by software sequence: a read
|
||||||
|
* operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read
|
||||||
|
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()).
|
||||||
|
* - UDR (UnderRun error) flag is cleared by a read operation to
|
||||||
|
* SPI_STATR register (SPI_I2S_GetFlagStatus()).
|
||||||
|
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
|
||||||
|
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a
|
||||||
|
* write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI).
|
||||||
|
* @return FlagStatus: SET or RESET.
|
||||||
|
*/
|
||||||
|
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
|
||||||
|
{
|
||||||
|
SPIx->STATR = (uint16_t)~SPI_I2S_FLAG;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
|
||||||
|
* SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
|
||||||
|
* SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
|
||||||
|
* SPI_I2S_IT_OVR - Overrun interrupt.
|
||||||
|
* SPI_IT_MODF - Mode Fault interrupt.
|
||||||
|
* SPI_IT_CRCERR - CRC Error interrupt.
|
||||||
|
* I2S_IT_UDR - Underrun Error interrupt.
|
||||||
|
*
|
||||||
|
* @return FlagStatus: SET or RESET.
|
||||||
|
*/
|
||||||
|
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
|
||||||
|
|
||||||
|
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||||
|
itmask = SPI_I2S_IT >> 4;
|
||||||
|
itmask = 0x01 << itmask;
|
||||||
|
enablestatus = (SPIx->CTLR2 & itmask);
|
||||||
|
|
||||||
|
if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
|
||||||
|
* SPI_IT_CRCERR - CRC Error interrupt.
|
||||||
|
* Note-
|
||||||
|
* - OVR (OverRun Error) interrupt pending bit is cleared by software
|
||||||
|
* sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData())
|
||||||
|
* followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()).
|
||||||
|
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
|
||||||
|
* operation to SPI_STATR register (SPI_I2S_GetITStatus()).
|
||||||
|
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
|
||||||
|
* a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus())
|
||||||
|
* followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable
|
||||||
|
* the SPI).
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
|
||||||
|
{
|
||||||
|
uint16_t itpos = 0;
|
||||||
|
|
||||||
|
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||||
|
SPIx->STATR = (uint16_t)~itpos;
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,783 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_usart.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.1
|
||||||
|
* Date : 2025/04/12
|
||||||
|
* Description : This file provides all the USART firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_usart.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* USART_Private_Defines */
|
||||||
|
#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */
|
||||||
|
#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */
|
||||||
|
|
||||||
|
#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
|
||||||
|
|
||||||
|
#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */
|
||||||
|
#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
|
||||||
|
#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */
|
||||||
|
#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */
|
||||||
|
#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */
|
||||||
|
|
||||||
|
#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */
|
||||||
|
#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
|
||||||
|
|
||||||
|
#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
|
||||||
|
#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */
|
||||||
|
#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */
|
||||||
|
|
||||||
|
#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */
|
||||||
|
#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */
|
||||||
|
|
||||||
|
#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
|
||||||
|
#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
|
||||||
|
|
||||||
|
#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
|
||||||
|
#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
|
||||||
|
|
||||||
|
#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
|
||||||
|
#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */
|
||||||
|
|
||||||
|
#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */
|
||||||
|
#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
|
||||||
|
#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
|
||||||
|
#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
|
||||||
|
#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the USARTx peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_DeInit(USART_TypeDef *USARTx)
|
||||||
|
{
|
||||||
|
if(USARTx == USART1)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
|
||||||
|
}
|
||||||
|
else if(USARTx == USART2)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
|
||||||
|
}
|
||||||
|
else if(USARTx == USART3)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
|
||||||
|
}
|
||||||
|
else if(USARTx == UART4)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
|
||||||
|
}
|
||||||
|
else if(USARTx == UART5)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
|
||||||
|
}
|
||||||
|
else if(USARTx == UART6)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, DISABLE);
|
||||||
|
}
|
||||||
|
else if(USARTx == UART7)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE);
|
||||||
|
}
|
||||||
|
else if(USARTx == UART8)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the USARTx peripheral according to the specified
|
||||||
|
* parameters in the USART_InitStruct.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_InitStruct - pointer to a USART_InitTypeDef structure
|
||||||
|
* that contains the configuration information for the specified
|
||||||
|
* USART peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0x00, apbclock = 0x00;
|
||||||
|
uint32_t integerdivider = 0x00;
|
||||||
|
uint32_t fractionaldivider = 0x00;
|
||||||
|
uint32_t usartxbase = 0;
|
||||||
|
RCC_ClocksTypeDef RCC_ClocksStatus;
|
||||||
|
|
||||||
|
if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
usartxbase = (uint32_t)USARTx;
|
||||||
|
tmpreg = USARTx->CTLR2;
|
||||||
|
tmpreg &= CTLR2_STOP_CLEAR_Mask;
|
||||||
|
tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
|
||||||
|
|
||||||
|
USARTx->CTLR2 = (uint16_t)tmpreg;
|
||||||
|
tmpreg = USARTx->CTLR1;
|
||||||
|
tmpreg &= CTLR1_CLEAR_Mask;
|
||||||
|
tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
|
||||||
|
USART_InitStruct->USART_Mode;
|
||||||
|
USARTx->CTLR1 = (uint16_t)tmpreg;
|
||||||
|
|
||||||
|
tmpreg = USARTx->CTLR3;
|
||||||
|
tmpreg &= CTLR3_CLEAR_Mask;
|
||||||
|
tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
|
||||||
|
USARTx->CTLR3 = (uint16_t)tmpreg;
|
||||||
|
|
||||||
|
RCC_GetClocksFreq(&RCC_ClocksStatus);
|
||||||
|
|
||||||
|
if(usartxbase == USART1_BASE)
|
||||||
|
{
|
||||||
|
apbclock = RCC_ClocksStatus.PCLK2_Frequency;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
apbclock = RCC_ClocksStatus.PCLK1_Frequency;
|
||||||
|
}
|
||||||
|
|
||||||
|
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
|
||||||
|
tmpreg = (integerdivider / 100) << 4;
|
||||||
|
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
|
||||||
|
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
|
||||||
|
USARTx->BRR = (uint16_t)tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each USART_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure
|
||||||
|
* which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_StructInit(USART_InitTypeDef *USART_InitStruct)
|
||||||
|
{
|
||||||
|
USART_InitStruct->USART_BaudRate = 9600;
|
||||||
|
USART_InitStruct->USART_WordLength = USART_WordLength_8b;
|
||||||
|
USART_InitStruct->USART_StopBits = USART_StopBits_1;
|
||||||
|
USART_InitStruct->USART_Parity = USART_Parity_No;
|
||||||
|
USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||||
|
USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_ClockInit
|
||||||
|
*
|
||||||
|
* @brief Initializes the USARTx peripheral Clock according to the
|
||||||
|
* specified parameters in the USART_ClockInitStruct .
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||||
|
* USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
|
||||||
|
* structure that contains the configuration information for the specified
|
||||||
|
* USART peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0x00;
|
||||||
|
|
||||||
|
tmpreg = USARTx->CTLR2;
|
||||||
|
tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
|
||||||
|
tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
|
||||||
|
USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
|
||||||
|
USARTx->CTLR2 = (uint16_t)tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_ClockStructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each USART_ClockStructInit member with its default value.
|
||||||
|
*
|
||||||
|
* @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||||
|
{
|
||||||
|
USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
|
||||||
|
USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
|
||||||
|
USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
|
||||||
|
USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified USART peripheral.
|
||||||
|
* reset values (Affects also the I2Ss).
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* NewState: ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
USARTx->CTLR1 |= CTLR1_UE_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
USARTx->CTLR1 &= CTLR1_UE_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified USART interrupts.
|
||||||
|
* reset values (Affects also the I2Ss).
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_IT - specifies the USART interrupt sources to be enabled or disabled.
|
||||||
|
* USART_IT_LBD - LIN Break detection interrupt.
|
||||||
|
* USART_IT_TXE - Transmit Data Register empty interrupt.
|
||||||
|
* USART_IT_TC - Transmission complete interrupt.
|
||||||
|
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||||
|
* USART_IT_IDLE - Idle line detection interrupt.
|
||||||
|
* USART_IT_PE - Parity Error interrupt.
|
||||||
|
* USART_IT_ERR - Error interrupt.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
|
||||||
|
uint32_t usartxbase = 0x00;
|
||||||
|
|
||||||
|
usartxbase = (uint32_t)USARTx;
|
||||||
|
usartreg = (((uint8_t)USART_IT) >> 0x05);
|
||||||
|
itpos = USART_IT & IT_Mask;
|
||||||
|
itmask = (((uint32_t)0x01) << itpos);
|
||||||
|
|
||||||
|
if(usartreg == 0x01)
|
||||||
|
{
|
||||||
|
usartxbase += 0x0C;
|
||||||
|
}
|
||||||
|
else if(usartreg == 0x02)
|
||||||
|
{
|
||||||
|
usartxbase += 0x10;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
usartxbase += 0x14;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
*(__IO uint32_t *)usartxbase |= itmask;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
*(__IO uint32_t *)usartxbase &= ~itmask;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_DMACmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the USART DMA interface.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_DMAReq - specifies the DMA request.
|
||||||
|
* USART_DMAReq_Tx - USART DMA transmit request.
|
||||||
|
* USART_DMAReq_Rx - USART DMA receive request.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 |= USART_DMAReq;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_SetAddress
|
||||||
|
*
|
||||||
|
* @brief Sets the address of the USART node.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_Address - Indicates the address of the USART node.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address)
|
||||||
|
{
|
||||||
|
USARTx->CTLR2 &= CTLR2_Address_Mask;
|
||||||
|
USARTx->CTLR2 |= USART_Address;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_WakeUpConfig
|
||||||
|
*
|
||||||
|
* @brief Selects the USART WakeUp method.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_WakeUp - specifies the USART wakeup method.
|
||||||
|
* USART_WakeUp_IdleLine - WakeUp by an idle line detection.
|
||||||
|
* USART_WakeUp_AddressMark - WakeUp by an address mark.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
|
||||||
|
{
|
||||||
|
USARTx->CTLR1 &= CTLR1_WAKE_Mask;
|
||||||
|
USARTx->CTLR1 |= USART_WakeUp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_ReceiverWakeUpCmd
|
||||||
|
*
|
||||||
|
* @brief Determines if the USART is in mute mode or not.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
USARTx->CTLR1 |= CTLR1_RWU_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
USARTx->CTLR1 &= CTLR1_RWU_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_LINBreakDetectLengthConfig
|
||||||
|
*
|
||||||
|
* @brief Sets the USART LIN Break detection length.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_LINBreakDetectLength - specifies the LIN break detection length.
|
||||||
|
* USART_LINBreakDetectLength_10b - 10-bit break detection.
|
||||||
|
* USART_LINBreakDetectLength_11b - 11-bit break detection.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
|
||||||
|
{
|
||||||
|
USARTx->CTLR2 &= CTLR2_LBDL_Mask;
|
||||||
|
USARTx->CTLR2 |= USART_LINBreakDetectLength;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_LINCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the USART LIN mode.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
USARTx->CTLR2 |= CTLR2_LINEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
USARTx->CTLR2 &= CTLR2_LINEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_SendData
|
||||||
|
*
|
||||||
|
* @brief Transmits single data through the USARTx peripheral.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* Data - the data to transmit.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data)
|
||||||
|
{
|
||||||
|
USARTx->DATAR = (Data & (uint16_t)0x01FF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_ReceiveData
|
||||||
|
*
|
||||||
|
* @brief Returns the most recent received data by the USARTx peripheral.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
*
|
||||||
|
* @return The received data.
|
||||||
|
*/
|
||||||
|
uint16_t USART_ReceiveData(USART_TypeDef *USARTx)
|
||||||
|
{
|
||||||
|
return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_SendBreak
|
||||||
|
*
|
||||||
|
* @brief Transmits break characters.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_SendBreak(USART_TypeDef *USARTx)
|
||||||
|
{
|
||||||
|
USARTx->CTLR1 |= CTLR1_SBK_Set;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_SetGuardTime
|
||||||
|
*
|
||||||
|
* @brief Sets the specified USART guard time.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_GuardTime - specifies the guard time.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
|
||||||
|
{
|
||||||
|
USARTx->GPR &= GPR_LSB_Mask;
|
||||||
|
USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_SetPrescaler
|
||||||
|
*
|
||||||
|
* @brief Sets the system clock prescaler.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_Prescaler - specifies the prescaler clock.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
|
||||||
|
{
|
||||||
|
USARTx->GPR &= GPR_MSB_Mask;
|
||||||
|
USARTx->GPR |= USART_Prescaler;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_SmartCardCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the USART Smart Card mode.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 |= CTLR3_SCEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 &= CTLR3_SCEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_SmartCardNACKCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables NACK transmission.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 |= CTLR3_NACK_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 &= CTLR3_NACK_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_HalfDuplexCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the USART Half Duplex communication.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 |= CTLR3_HDSEL_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_IrDAConfig
|
||||||
|
*
|
||||||
|
* @brief Configures the USART's IrDA interface.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_IrDAMode - specifies the IrDA mode.
|
||||||
|
* USART_IrDAMode_LowPower.
|
||||||
|
* USART_IrDAMode_Normal.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 &= CTLR3_IRLP_Mask;
|
||||||
|
USARTx->CTLR3 |= USART_IrDAMode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_IrDACmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the USART's IrDA interface.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 |= CTLR3_IREN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
USARTx->CTLR3 &= CTLR3_IREN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified USART flag is set or not.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_FLAG - specifies the flag to check.
|
||||||
|
* USART_FLAG_LBD - LIN Break detection flag.
|
||||||
|
* USART_FLAG_TXE - Transmit data register empty flag.
|
||||||
|
* USART_FLAG_TC - Transmission Complete flag.
|
||||||
|
* USART_FLAG_RXNE - Receive data register not empty flag.
|
||||||
|
* USART_FLAG_IDLE - Idle Line detection flag.
|
||||||
|
* USART_FLAG_ORE - OverRun Error flag.
|
||||||
|
* USART_FLAG_NE - Noise Error flag.
|
||||||
|
* USART_FLAG_FE - Framing Error flag.
|
||||||
|
* USART_FLAG_PE - Parity Error flag.
|
||||||
|
*
|
||||||
|
* @return bitstatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the USARTx's pending flags.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_FLAG - specifies the flag to clear.
|
||||||
|
* USART_FLAG_LBD - LIN Break detection flag.
|
||||||
|
* USART_FLAG_TC - Transmission Complete flag.
|
||||||
|
* USART_FLAG_RXNE - Receive data register not empty flag.
|
||||||
|
* Note-
|
||||||
|
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||||
|
* error) and IDLE (Idle line detected) flags are cleared by software
|
||||||
|
* sequence: a read operation to USART_STATR register (USART_GetFlagStatus())
|
||||||
|
* followed by a read operation to USART_DATAR register (USART_ReceiveData()).
|
||||||
|
* - RXNE flag can be also cleared by a read to the USART_DATAR register
|
||||||
|
* (USART_ReceiveData()).
|
||||||
|
* - TC flag can be also cleared by software sequence: a read operation to
|
||||||
|
* USART_STATR register (USART_GetFlagStatus()) followed by a write operation
|
||||||
|
* to USART_DATAR register (USART_SendData()).
|
||||||
|
* - TXE flag is cleared only by a write to the USART_DATAR register
|
||||||
|
* (USART_SendData()).
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
|
||||||
|
{
|
||||||
|
|
||||||
|
USARTx->STATR = (uint16_t)~USART_FLAG;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified USART interrupt has occurred or not.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_IT - specifies the USART interrupt source to check.
|
||||||
|
* USART_IT_LBD - LIN Break detection interrupt.
|
||||||
|
* USART_IT_TXE - Tansmit Data Register empty interrupt.
|
||||||
|
* USART_IT_TC - Transmission complete interrupt.
|
||||||
|
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||||
|
* USART_IT_IDLE - Idle line detection interrupt.
|
||||||
|
* USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
|
||||||
|
* USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
|
||||||
|
* USART_IT_NE - Noise Error interrupt.
|
||||||
|
* USART_IT_FE - Framing Error interrupt.
|
||||||
|
* USART_IT_PE - Parity Error interrupt.
|
||||||
|
*
|
||||||
|
* @return bitstatus: SET or RESET.
|
||||||
|
*/
|
||||||
|
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
|
||||||
|
{
|
||||||
|
uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
usartreg = (((uint8_t)USART_IT) >> 0x05);
|
||||||
|
itmask = USART_IT & IT_Mask;
|
||||||
|
itmask = (uint32_t)0x01 << itmask;
|
||||||
|
|
||||||
|
if(usartreg == 0x01)
|
||||||
|
{
|
||||||
|
itmask &= USARTx->CTLR1;
|
||||||
|
}
|
||||||
|
else if(usartreg == 0x02)
|
||||||
|
{
|
||||||
|
itmask &= USARTx->CTLR2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
itmask &= USARTx->CTLR3;
|
||||||
|
}
|
||||||
|
|
||||||
|
bitpos = USART_IT >> 0x08;
|
||||||
|
bitpos = (uint32_t)0x01 << bitpos;
|
||||||
|
bitpos &= USARTx->STATR;
|
||||||
|
|
||||||
|
if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the USARTx's interrupt pending bits.
|
||||||
|
*
|
||||||
|
* @param USARTx - where x can be 1 to 3 to select the USART peripheral.
|
||||||
|
* UARTx where x can be 4 to 8 to select the UART peripheral.
|
||||||
|
* USART_IT - specifies the interrupt pending bit to clear.
|
||||||
|
* USART_IT_LBD - LIN Break detection interrupt.
|
||||||
|
* USART_IT_TC - Transmission complete interrupt.
|
||||||
|
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||||
|
* Note-
|
||||||
|
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||||
|
* error) and IDLE (Idle line detected) pending bits are cleared by
|
||||||
|
* software sequence: a read operation to USART_STATR register
|
||||||
|
* (USART_GetITStatus()) followed by a read operation to USART_DATAR register
|
||||||
|
* (USART_ReceiveData()).
|
||||||
|
* - RXNE pending bit can be also cleared by a read to the USART_DATAR register
|
||||||
|
* (USART_ReceiveData()).
|
||||||
|
* - TC pending bit can be also cleared by software sequence: a read
|
||||||
|
* operation to USART_STATR register (USART_GetITStatus()) followed by a write
|
||||||
|
* operation to USART_DATAR register (USART_SendData()).
|
||||||
|
* - TXE pending bit is cleared only by a write to the USART_DATAR register
|
||||||
|
* (USART_SendData()).
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
|
||||||
|
{
|
||||||
|
uint16_t bitpos = 0x00, itmask = 0x00;
|
||||||
|
|
||||||
|
bitpos = USART_IT >> 0x08;
|
||||||
|
itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
|
||||||
|
USARTx->STATR = (uint16_t)~itmask;
|
||||||
|
}
|
||||||
@@ -0,0 +1,141 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_wwdg.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the WWDG firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_wwdg.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* CTLR register bit mask */
|
||||||
|
#define CTLR_WDGA_Set ((uint32_t)0x00000080)
|
||||||
|
|
||||||
|
/* CFGR register bit mask */
|
||||||
|
#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
|
||||||
|
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
|
||||||
|
#define BIT_Mask ((uint8_t)0x7F)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WWDG_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the WWDG peripheral registers to their default reset values
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WWDG_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WWDG_SetPrescaler
|
||||||
|
*
|
||||||
|
* @brief Sets the WWDG Prescaler
|
||||||
|
*
|
||||||
|
* @param WWDG_Prescaler - specifies the WWDG Prescaler
|
||||||
|
* WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
|
||||||
|
* WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
|
||||||
|
* WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
|
||||||
|
* WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
|
||||||
|
tmpreg |= WWDG_Prescaler;
|
||||||
|
WWDG->CFGR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WWDG_SetWindowValue
|
||||||
|
*
|
||||||
|
* @brief Sets the WWDG window value
|
||||||
|
*
|
||||||
|
* @param WindowValue - specifies the window value to be compared to the
|
||||||
|
* downcounter,which must be lower than 0x80
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WWDG_SetWindowValue(uint8_t WindowValue)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = WWDG->CFGR & CFGR_W_Mask;
|
||||||
|
|
||||||
|
tmpreg |= WindowValue & (uint32_t)BIT_Mask;
|
||||||
|
|
||||||
|
WWDG->CFGR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WWDG_EnableIT
|
||||||
|
*
|
||||||
|
* @brief Enables the WWDG Early Wakeup interrupt(EWI)
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WWDG_EnableIT(void)
|
||||||
|
{
|
||||||
|
WWDG->CFGR |= (1 << 9);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WWDG_SetCounter
|
||||||
|
*
|
||||||
|
* @brief Sets the WWDG counter value
|
||||||
|
*
|
||||||
|
* @param Counter - specifies the watchdog counter value,which must be a
|
||||||
|
* number between 0x40 and 0x7F
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WWDG_SetCounter(uint8_t Counter)
|
||||||
|
{
|
||||||
|
WWDG->CTLR = Counter & BIT_Mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WWDG_Enable
|
||||||
|
*
|
||||||
|
* @brief Enables WWDG and load the counter value
|
||||||
|
*
|
||||||
|
* @param Counter - specifies the watchdog counter value,which must be a
|
||||||
|
* number between 0x40 and 0x7F
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WWDG_Enable(uint8_t Counter)
|
||||||
|
{
|
||||||
|
WWDG->CTLR = CTLR_WDGA_Set | Counter;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WWDG_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the Early Wakeup interrupt flag is set or not
|
||||||
|
*
|
||||||
|
* @return The new state of the Early Wakeup interrupt flag (SET or RESET)
|
||||||
|
*/
|
||||||
|
FlagStatus WWDG_GetFlagStatus(void)
|
||||||
|
{
|
||||||
|
return (FlagStatus)(WWDG->STATR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn WWDG_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears Early Wakeup interrupt flag
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void WWDG_ClearFlag(void)
|
||||||
|
{
|
||||||
|
WWDG->STATR = (uint32_t)RESET;
|
||||||
|
}
|
||||||
@@ -0,0 +1,356 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : startup_ch32v30x_D8.s
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.2
|
||||||
|
* Date : 2025/03/06
|
||||||
|
* Description : CH32V303x vector table for eclipse toolchain.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.section .init,"ax",@progbits
|
||||||
|
.global _start
|
||||||
|
.align 1
|
||||||
|
_start:
|
||||||
|
j handle_reset
|
||||||
|
|
||||||
|
.section .vector,"ax",@progbits
|
||||||
|
.align 1
|
||||||
|
_vector_base:
|
||||||
|
.option norvc;
|
||||||
|
.word _start
|
||||||
|
.word 0
|
||||||
|
.word NMI_Handler /* NMI */
|
||||||
|
.word HardFault_Handler /* Hard Fault */
|
||||||
|
.word 0
|
||||||
|
.word Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||||
|
.word Break_Point_Handler /* Break Point */
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SysTick_Handler /* SysTick */
|
||||||
|
.word 0
|
||||||
|
.word SW_Handler /* SW */
|
||||||
|
.word 0
|
||||||
|
/* External Interrupts */
|
||||||
|
.word WWDG_IRQHandler /* Window Watchdog */
|
||||||
|
.word PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||||
|
.word TAMPER_IRQHandler /* TAMPER */
|
||||||
|
.word RTC_IRQHandler /* RTC */
|
||||||
|
.word FLASH_IRQHandler /* Flash */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_IRQHandler /* EXTI Line 0 */
|
||||||
|
.word EXTI1_IRQHandler /* EXTI Line 1 */
|
||||||
|
.word EXTI2_IRQHandler /* EXTI Line 2 */
|
||||||
|
.word EXTI3_IRQHandler /* EXTI Line 3 */
|
||||||
|
.word EXTI4_IRQHandler /* EXTI Line 4 */
|
||||||
|
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||||
|
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||||
|
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||||
|
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||||
|
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||||
|
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||||
|
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||||
|
.word ADC1_2_IRQHandler /* ADC1_2 */
|
||||||
|
.word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
|
||||||
|
.word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
|
||||||
|
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||||
|
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||||
|
.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||||
|
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||||
|
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||||
|
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word USART3_IRQHandler /* USART3 */
|
||||||
|
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||||
|
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||||
|
.word 0
|
||||||
|
.word TIM8_BRK_IRQHandler /* TIM8 Break */
|
||||||
|
.word TIM8_UP_IRQHandler /* TIM8 Update */
|
||||||
|
.word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
|
||||||
|
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.word RNG_IRQHandler /* RNG */
|
||||||
|
.word 0
|
||||||
|
.word SDIO_IRQHandler /* SDIO */
|
||||||
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
|
.word UART4_IRQHandler /* UART4 */
|
||||||
|
.word UART5_IRQHandler /* UART5 */
|
||||||
|
.word TIM6_IRQHandler /* TIM6 */
|
||||||
|
.word TIM7_IRQHandler /* TIM7 */
|
||||||
|
.word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
|
||||||
|
.word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
|
||||||
|
.word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
|
||||||
|
.word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
|
||||||
|
.word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word USBFS_IRQHandler /* USBFS */
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word UART6_IRQHandler /* UART6 */
|
||||||
|
.word UART7_IRQHandler /* UART7 */
|
||||||
|
.word UART8_IRQHandler /* UART8 */
|
||||||
|
.word TIM9_BRK_IRQHandler /* TIM9 Break */
|
||||||
|
.word TIM9_UP_IRQHandler /* TIM9 Update */
|
||||||
|
.word TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */
|
||||||
|
.word TIM9_CC_IRQHandler /* TIM9 Capture Compare */
|
||||||
|
.word TIM10_BRK_IRQHandler /* TIM10 Break */
|
||||||
|
.word TIM10_UP_IRQHandler /* TIM10 Update */
|
||||||
|
.word TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */
|
||||||
|
.word TIM10_CC_IRQHandler /* TIM10 Capture Compare */
|
||||||
|
.word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
|
||||||
|
.word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
|
||||||
|
.word DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
|
||||||
|
.word DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */
|
||||||
|
.word DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */
|
||||||
|
.word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */
|
||||||
|
|
||||||
|
.option rvc;
|
||||||
|
.section .text.vector_handler, "ax", @progbits
|
||||||
|
.weak NMI_Handler /* NMI */
|
||||||
|
.weak HardFault_Handler /* Hard Fault */
|
||||||
|
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||||
|
.weak Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||||
|
.weak Break_Point_Handler /* Break Point */
|
||||||
|
.weak SysTick_Handler /* SysTick */
|
||||||
|
.weak SW_Handler /* SW */
|
||||||
|
.weak WWDG_IRQHandler /* Window Watchdog */
|
||||||
|
.weak PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||||
|
.weak TAMPER_IRQHandler /* TAMPER */
|
||||||
|
.weak RTC_IRQHandler /* RTC */
|
||||||
|
.weak FLASH_IRQHandler /* Flash */
|
||||||
|
.weak RCC_IRQHandler /* RCC */
|
||||||
|
.weak EXTI0_IRQHandler /* EXTI Line 0 */
|
||||||
|
.weak EXTI1_IRQHandler /* EXTI Line 1 */
|
||||||
|
.weak EXTI2_IRQHandler /* EXTI Line 2 */
|
||||||
|
.weak EXTI3_IRQHandler /* EXTI Line 3 */
|
||||||
|
.weak EXTI4_IRQHandler /* EXTI Line 4 */
|
||||||
|
.weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||||
|
.weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||||
|
.weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||||
|
.weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||||
|
.weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||||
|
.weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||||
|
.weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||||
|
.weak ADC1_2_IRQHandler /* ADC1_2 */
|
||||||
|
.weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
|
||||||
|
.weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
|
||||||
|
.weak CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||||
|
.weak CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||||
|
.weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||||
|
.weak TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||||
|
.weak TIM1_UP_IRQHandler /* TIM1 Update */
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||||
|
.weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.weak TIM2_IRQHandler /* TIM2 */
|
||||||
|
.weak TIM3_IRQHandler /* TIM3 */
|
||||||
|
.weak TIM4_IRQHandler /* TIM4 */
|
||||||
|
.weak I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.weak I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.weak I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.weak I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.weak SPI1_IRQHandler /* SPI1 */
|
||||||
|
.weak SPI2_IRQHandler /* SPI2 */
|
||||||
|
.weak USART1_IRQHandler /* USART1 */
|
||||||
|
.weak USART2_IRQHandler /* USART2 */
|
||||||
|
.weak USART3_IRQHandler /* USART3 */
|
||||||
|
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||||
|
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||||
|
.weak TIM8_BRK_IRQHandler /* TIM8 Break */
|
||||||
|
.weak TIM8_UP_IRQHandler /* TIM8 Update */
|
||||||
|
.weak TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
|
||||||
|
.weak TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.weak RNG_IRQHandler /* RNG */
|
||||||
|
.weak SDIO_IRQHandler /* SDIO */
|
||||||
|
.weak TIM5_IRQHandler /* TIM5 */
|
||||||
|
.weak SPI3_IRQHandler /* SPI3 */
|
||||||
|
.weak UART4_IRQHandler /* UART4 */
|
||||||
|
.weak UART5_IRQHandler /* UART5 */
|
||||||
|
.weak TIM6_IRQHandler /* TIM6 */
|
||||||
|
.weak TIM7_IRQHandler /* TIM7 */
|
||||||
|
.weak DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
|
||||||
|
.weak DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
|
||||||
|
.weak DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
|
||||||
|
.weak DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
|
||||||
|
.weak DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
|
||||||
|
.weak USBFS_IRQHandler /* USBFS */
|
||||||
|
.weak UART6_IRQHandler /* UART6 */
|
||||||
|
.weak UART7_IRQHandler /* UART7 */
|
||||||
|
.weak UART8_IRQHandler /* UART8 */
|
||||||
|
.weak TIM9_BRK_IRQHandler /* TIM9 Break */
|
||||||
|
.weak TIM9_UP_IRQHandler /* TIM9 Update */
|
||||||
|
.weak TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */
|
||||||
|
.weak TIM9_CC_IRQHandler /* TIM9 Capture Compare */
|
||||||
|
.weak TIM10_BRK_IRQHandler /* TIM10 Break */
|
||||||
|
.weak TIM10_UP_IRQHandler /* TIM10 Update */
|
||||||
|
.weak TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */
|
||||||
|
.weak TIM10_CC_IRQHandler /* TIM10 Capture Compare */
|
||||||
|
.weak DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
|
||||||
|
.weak DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
|
||||||
|
.weak DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
|
||||||
|
.weak DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */
|
||||||
|
.weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */
|
||||||
|
.weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */
|
||||||
|
|
||||||
|
NMI_Handler:
|
||||||
|
HardFault_Handler:
|
||||||
|
Ecall_M_Mode_Handler:
|
||||||
|
Ecall_U_Mode_Handler:
|
||||||
|
Break_Point_Handler:
|
||||||
|
SysTick_Handler:
|
||||||
|
SW_Handler:
|
||||||
|
WWDG_IRQHandler:
|
||||||
|
PVD_IRQHandler:
|
||||||
|
TAMPER_IRQHandler:
|
||||||
|
RTC_IRQHandler:
|
||||||
|
FLASH_IRQHandler:
|
||||||
|
RCC_IRQHandler:
|
||||||
|
EXTI0_IRQHandler:
|
||||||
|
EXTI1_IRQHandler:
|
||||||
|
EXTI2_IRQHandler:
|
||||||
|
EXTI3_IRQHandler:
|
||||||
|
EXTI4_IRQHandler:
|
||||||
|
DMA1_Channel1_IRQHandler:
|
||||||
|
DMA1_Channel2_IRQHandler:
|
||||||
|
DMA1_Channel3_IRQHandler:
|
||||||
|
DMA1_Channel4_IRQHandler:
|
||||||
|
DMA1_Channel5_IRQHandler:
|
||||||
|
DMA1_Channel6_IRQHandler:
|
||||||
|
DMA1_Channel7_IRQHandler:
|
||||||
|
ADC1_2_IRQHandler:
|
||||||
|
USB_HP_CAN1_TX_IRQHandler:
|
||||||
|
USB_LP_CAN1_RX0_IRQHandler:
|
||||||
|
CAN1_RX1_IRQHandler:
|
||||||
|
CAN1_SCE_IRQHandler:
|
||||||
|
EXTI9_5_IRQHandler:
|
||||||
|
TIM1_BRK_IRQHandler:
|
||||||
|
TIM1_UP_IRQHandler:
|
||||||
|
TIM1_TRG_COM_IRQHandler:
|
||||||
|
TIM1_CC_IRQHandler:
|
||||||
|
TIM2_IRQHandler:
|
||||||
|
TIM3_IRQHandler:
|
||||||
|
TIM4_IRQHandler:
|
||||||
|
I2C1_EV_IRQHandler:
|
||||||
|
I2C1_ER_IRQHandler:
|
||||||
|
I2C2_EV_IRQHandler:
|
||||||
|
I2C2_ER_IRQHandler:
|
||||||
|
SPI1_IRQHandler:
|
||||||
|
SPI2_IRQHandler:
|
||||||
|
USART1_IRQHandler:
|
||||||
|
USART2_IRQHandler:
|
||||||
|
USART3_IRQHandler:
|
||||||
|
EXTI15_10_IRQHandler:
|
||||||
|
RTCAlarm_IRQHandler:
|
||||||
|
TIM8_BRK_IRQHandler:
|
||||||
|
TIM8_UP_IRQHandler:
|
||||||
|
TIM8_TRG_COM_IRQHandler:
|
||||||
|
TIM8_CC_IRQHandler:
|
||||||
|
RNG_IRQHandler:
|
||||||
|
SDIO_IRQHandler:
|
||||||
|
TIM5_IRQHandler:
|
||||||
|
SPI3_IRQHandler:
|
||||||
|
UART4_IRQHandler:
|
||||||
|
UART5_IRQHandler:
|
||||||
|
TIM6_IRQHandler:
|
||||||
|
TIM7_IRQHandler:
|
||||||
|
DMA2_Channel1_IRQHandler:
|
||||||
|
DMA2_Channel2_IRQHandler:
|
||||||
|
DMA2_Channel3_IRQHandler:
|
||||||
|
DMA2_Channel4_IRQHandler:
|
||||||
|
DMA2_Channel5_IRQHandler:
|
||||||
|
USBFS_IRQHandler:
|
||||||
|
UART6_IRQHandler:
|
||||||
|
UART7_IRQHandler:
|
||||||
|
UART8_IRQHandler:
|
||||||
|
TIM9_BRK_IRQHandler:
|
||||||
|
TIM9_UP_IRQHandler:
|
||||||
|
TIM9_TRG_COM_IRQHandler:
|
||||||
|
TIM9_CC_IRQHandler:
|
||||||
|
TIM10_BRK_IRQHandler:
|
||||||
|
TIM10_UP_IRQHandler:
|
||||||
|
TIM10_TRG_COM_IRQHandler:
|
||||||
|
TIM10_CC_IRQHandler:
|
||||||
|
DMA2_Channel6_IRQHandler:
|
||||||
|
DMA2_Channel7_IRQHandler:
|
||||||
|
DMA2_Channel8_IRQHandler:
|
||||||
|
DMA2_Channel9_IRQHandler:
|
||||||
|
DMA2_Channel10_IRQHandler:
|
||||||
|
DMA2_Channel11_IRQHandler:
|
||||||
|
1:
|
||||||
|
j 1b
|
||||||
|
|
||||||
|
.section .text.handle_reset,"ax",@progbits
|
||||||
|
.weak handle_reset
|
||||||
|
.align 1
|
||||||
|
handle_reset:
|
||||||
|
.option push
|
||||||
|
.option norelax
|
||||||
|
la gp, __global_pointer$
|
||||||
|
.option pop
|
||||||
|
|
||||||
|
la sp, _eusrstack
|
||||||
|
|
||||||
|
/* Load data section from flash to RAM */
|
||||||
|
la a0, _data_lma
|
||||||
|
la a1, _data_vma
|
||||||
|
la a2, _edata
|
||||||
|
bgeu a1, a2, 2f
|
||||||
|
1:
|
||||||
|
lw t0, (a0)
|
||||||
|
sw t0, (a1)
|
||||||
|
addi a0, a0, 4
|
||||||
|
addi a1, a1, 4
|
||||||
|
bltu a1, a2, 1b
|
||||||
|
2:
|
||||||
|
/* Clear bss section */
|
||||||
|
la a0, _sbss
|
||||||
|
la a1, _ebss
|
||||||
|
bgeu a0, a1, 2f
|
||||||
|
1:
|
||||||
|
sw zero, (a0)
|
||||||
|
addi a0, a0, 4
|
||||||
|
bltu a0, a1, 1b
|
||||||
|
2:
|
||||||
|
/* Configure pipelining and instruction prediction */
|
||||||
|
li t0, 0x1f
|
||||||
|
csrw 0xbc0, t0
|
||||||
|
/* Enable interrupt nesting and hardware stack */
|
||||||
|
li t0, 0x0b
|
||||||
|
csrw 0x804, t0
|
||||||
|
/* Enable floating point and global interrupt, configure privileged mode */
|
||||||
|
li t0, 0x6088
|
||||||
|
csrw mstatus, t0
|
||||||
|
/* Configure the interrupt vector table recognition mode and entry address mode */
|
||||||
|
la t0, _vector_base
|
||||||
|
ori t0, t0, 3
|
||||||
|
csrw mtvec, t0
|
||||||
|
|
||||||
|
jal SystemInit
|
||||||
|
la t0, main
|
||||||
|
csrw mepc, t0
|
||||||
|
mret
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,374 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : startup_ch32v30x_D8C.s
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.1
|
||||||
|
* Date : 2025/04/06
|
||||||
|
* Description : CH32V307x-CH32V305x vector table for eclipse toolchain.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.section .init,"ax",@progbits
|
||||||
|
.global _start
|
||||||
|
.align 1
|
||||||
|
_start:
|
||||||
|
j handle_reset
|
||||||
|
|
||||||
|
.section .vector,"ax",@progbits
|
||||||
|
.align 1
|
||||||
|
_vector_base:
|
||||||
|
.option norvc;
|
||||||
|
.word _start
|
||||||
|
.word 0
|
||||||
|
.word NMI_Handler /* NMI */
|
||||||
|
.word HardFault_Handler /* Hard Fault */
|
||||||
|
.word 0
|
||||||
|
.word Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||||
|
.word Break_Point_Handler /* Break Point */
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SysTick_Handler /* SysTick */
|
||||||
|
.word 0
|
||||||
|
.word SW_Handler /* SW */
|
||||||
|
.word 0
|
||||||
|
/* External Interrupts */
|
||||||
|
.word WWDG_IRQHandler /* Window Watchdog */
|
||||||
|
.word PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||||
|
.word TAMPER_IRQHandler /* TAMPER */
|
||||||
|
.word RTC_IRQHandler /* RTC */
|
||||||
|
.word FLASH_IRQHandler /* Flash */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_IRQHandler /* EXTI Line 0 */
|
||||||
|
.word EXTI1_IRQHandler /* EXTI Line 1 */
|
||||||
|
.word EXTI2_IRQHandler /* EXTI Line 2 */
|
||||||
|
.word EXTI3_IRQHandler /* EXTI Line 3 */
|
||||||
|
.word EXTI4_IRQHandler /* EXTI Line 4 */
|
||||||
|
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||||
|
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||||
|
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||||
|
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||||
|
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||||
|
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||||
|
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||||
|
.word ADC1_2_IRQHandler /* ADC1_2 */
|
||||||
|
.word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
|
||||||
|
.word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
|
||||||
|
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||||
|
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||||
|
.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||||
|
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||||
|
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||||
|
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word USART3_IRQHandler /* USART3 */
|
||||||
|
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||||
|
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||||
|
.word USBWakeUp_IRQHandler /* USB Wakeup from suspend */
|
||||||
|
.word TIM8_BRK_IRQHandler /* TIM8 Break */
|
||||||
|
.word TIM8_UP_IRQHandler /* TIM8 Update */
|
||||||
|
.word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
|
||||||
|
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.word RNG_IRQHandler /* RNG */
|
||||||
|
.word 0
|
||||||
|
.word SDIO_IRQHandler /* SDIO */
|
||||||
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
|
.word UART4_IRQHandler /* UART4 */
|
||||||
|
.word UART5_IRQHandler /* UART5 */
|
||||||
|
.word TIM6_IRQHandler /* TIM6 */
|
||||||
|
.word TIM7_IRQHandler /* TIM7 */
|
||||||
|
.word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
|
||||||
|
.word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
|
||||||
|
.word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
|
||||||
|
.word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
|
||||||
|
.word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
|
||||||
|
.word ETH_IRQHandler /* ETH */
|
||||||
|
.word ETH_WKUP_IRQHandler /* ETH WakeUp */
|
||||||
|
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||||
|
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||||
|
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||||
|
.word CAN2_SCE_IRQHandler /* CAN2 SCE */
|
||||||
|
.word USBFS_IRQHandler /* USBFS */
|
||||||
|
.word USBHSWakeup_IRQHandler /* USBHS Wakeup */
|
||||||
|
.word USBHS_IRQHandler /* USBHS */
|
||||||
|
.word DVP_IRQHandler /* DVP */
|
||||||
|
.word UART6_IRQHandler /* UART6 */
|
||||||
|
.word UART7_IRQHandler /* UART7 */
|
||||||
|
.word UART8_IRQHandler /* UART8 */
|
||||||
|
.word TIM9_BRK_IRQHandler /* TIM9 Break */
|
||||||
|
.word TIM9_UP_IRQHandler /* TIM9 Update */
|
||||||
|
.word TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */
|
||||||
|
.word TIM9_CC_IRQHandler /* TIM9 Capture Compare */
|
||||||
|
.word TIM10_BRK_IRQHandler /* TIM10 Break */
|
||||||
|
.word TIM10_UP_IRQHandler /* TIM10 Update */
|
||||||
|
.word TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */
|
||||||
|
.word TIM10_CC_IRQHandler /* TIM10 Capture Compare */
|
||||||
|
.word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
|
||||||
|
.word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
|
||||||
|
.word DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
|
||||||
|
.word DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */
|
||||||
|
.word DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */
|
||||||
|
.word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */
|
||||||
|
|
||||||
|
.option rvc;
|
||||||
|
.section .text.vector_handler, "ax", @progbits
|
||||||
|
.weak NMI_Handler /* NMI */
|
||||||
|
.weak HardFault_Handler /* Hard Fault */
|
||||||
|
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||||
|
.weak Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||||
|
.weak Break_Point_Handler /* Break Point */
|
||||||
|
.weak SysTick_Handler /* SysTick */
|
||||||
|
.weak SW_Handler /* SW */
|
||||||
|
.weak WWDG_IRQHandler /* Window Watchdog */
|
||||||
|
.weak PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||||
|
.weak TAMPER_IRQHandler /* TAMPER */
|
||||||
|
.weak RTC_IRQHandler /* RTC */
|
||||||
|
.weak FLASH_IRQHandler /* Flash */
|
||||||
|
.weak RCC_IRQHandler /* RCC */
|
||||||
|
.weak EXTI0_IRQHandler /* EXTI Line 0 */
|
||||||
|
.weak EXTI1_IRQHandler /* EXTI Line 1 */
|
||||||
|
.weak EXTI2_IRQHandler /* EXTI Line 2 */
|
||||||
|
.weak EXTI3_IRQHandler /* EXTI Line 3 */
|
||||||
|
.weak EXTI4_IRQHandler /* EXTI Line 4 */
|
||||||
|
.weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||||
|
.weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||||
|
.weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||||
|
.weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||||
|
.weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||||
|
.weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||||
|
.weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||||
|
.weak ADC1_2_IRQHandler /* ADC1_2 */
|
||||||
|
.weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
|
||||||
|
.weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
|
||||||
|
.weak CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||||
|
.weak CAN1_SCE_IRQHandler /* CAN1 SCE */
|
||||||
|
.weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||||
|
.weak TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||||
|
.weak TIM1_UP_IRQHandler /* TIM1 Update */
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||||
|
.weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.weak TIM2_IRQHandler /* TIM2 */
|
||||||
|
.weak TIM3_IRQHandler /* TIM3 */
|
||||||
|
.weak TIM4_IRQHandler /* TIM4 */
|
||||||
|
.weak I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.weak I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.weak I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.weak I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.weak SPI1_IRQHandler /* SPI1 */
|
||||||
|
.weak SPI2_IRQHandler /* SPI2 */
|
||||||
|
.weak USART1_IRQHandler /* USART1 */
|
||||||
|
.weak USART2_IRQHandler /* USART2 */
|
||||||
|
.weak USART3_IRQHandler /* USART3 */
|
||||||
|
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||||
|
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||||
|
.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
|
||||||
|
.weak TIM8_BRK_IRQHandler /* TIM8 Break */
|
||||||
|
.weak TIM8_UP_IRQHandler /* TIM8 Update */
|
||||||
|
.weak TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */
|
||||||
|
.weak TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.weak RNG_IRQHandler /* RNG */
|
||||||
|
.weak SDIO_IRQHandler /* SDIO */
|
||||||
|
.weak TIM5_IRQHandler /* TIM5 */
|
||||||
|
.weak SPI3_IRQHandler /* SPI3 */
|
||||||
|
.weak UART4_IRQHandler /* UART4 */
|
||||||
|
.weak UART5_IRQHandler /* UART5 */
|
||||||
|
.weak TIM6_IRQHandler /* TIM6 */
|
||||||
|
.weak TIM7_IRQHandler /* TIM7 */
|
||||||
|
.weak DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */
|
||||||
|
.weak DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */
|
||||||
|
.weak DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */
|
||||||
|
.weak DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */
|
||||||
|
.weak DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */
|
||||||
|
.weak ETH_IRQHandler /* ETH */
|
||||||
|
.weak ETH_WKUP_IRQHandler /* ETH WakeUp */
|
||||||
|
.weak CAN2_TX_IRQHandler /* CAN2 TX */
|
||||||
|
.weak CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||||
|
.weak CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||||
|
.weak CAN2_SCE_IRQHandler /* CAN2 SCE */
|
||||||
|
.weak USBFS_IRQHandler /* USBFS */
|
||||||
|
.weak USBHSWakeup_IRQHandler /* USBHS Wakeup */
|
||||||
|
.weak USBHS_IRQHandler /* USBHS */
|
||||||
|
.weak DVP_IRQHandler /* DVP */
|
||||||
|
.weak UART6_IRQHandler /* UART6 */
|
||||||
|
.weak UART7_IRQHandler /* UART7 */
|
||||||
|
.weak UART8_IRQHandler /* UART8 */
|
||||||
|
.weak TIM9_BRK_IRQHandler /* TIM9 Break */
|
||||||
|
.weak TIM9_UP_IRQHandler /* TIM9 Update */
|
||||||
|
.weak TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */
|
||||||
|
.weak TIM9_CC_IRQHandler /* TIM9 Capture Compare */
|
||||||
|
.weak TIM10_BRK_IRQHandler /* TIM10 Break */
|
||||||
|
.weak TIM10_UP_IRQHandler /* TIM10 Update */
|
||||||
|
.weak TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */
|
||||||
|
.weak TIM10_CC_IRQHandler /* TIM10 Capture Compare */
|
||||||
|
.weak DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */
|
||||||
|
.weak DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */
|
||||||
|
.weak DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */
|
||||||
|
.weak DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */
|
||||||
|
.weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */
|
||||||
|
.weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */
|
||||||
|
|
||||||
|
NMI_Handler:
|
||||||
|
HardFault_Handler:
|
||||||
|
Ecall_M_Mode_Handler:
|
||||||
|
Ecall_U_Mode_Handler:
|
||||||
|
Break_Point_Handler:
|
||||||
|
SysTick_Handler:
|
||||||
|
SW_Handler:
|
||||||
|
WWDG_IRQHandler:
|
||||||
|
PVD_IRQHandler:
|
||||||
|
TAMPER_IRQHandler:
|
||||||
|
RTC_IRQHandler:
|
||||||
|
FLASH_IRQHandler:
|
||||||
|
RCC_IRQHandler:
|
||||||
|
EXTI0_IRQHandler:
|
||||||
|
EXTI1_IRQHandler:
|
||||||
|
EXTI2_IRQHandler:
|
||||||
|
EXTI3_IRQHandler:
|
||||||
|
EXTI4_IRQHandler:
|
||||||
|
DMA1_Channel1_IRQHandler:
|
||||||
|
DMA1_Channel2_IRQHandler:
|
||||||
|
DMA1_Channel3_IRQHandler:
|
||||||
|
DMA1_Channel4_IRQHandler:
|
||||||
|
DMA1_Channel5_IRQHandler:
|
||||||
|
DMA1_Channel6_IRQHandler:
|
||||||
|
DMA1_Channel7_IRQHandler:
|
||||||
|
ADC1_2_IRQHandler:
|
||||||
|
USB_HP_CAN1_TX_IRQHandler:
|
||||||
|
USB_LP_CAN1_RX0_IRQHandler:
|
||||||
|
CAN1_RX1_IRQHandler:
|
||||||
|
CAN1_SCE_IRQHandler:
|
||||||
|
EXTI9_5_IRQHandler:
|
||||||
|
TIM1_BRK_IRQHandler:
|
||||||
|
TIM1_UP_IRQHandler:
|
||||||
|
TIM1_TRG_COM_IRQHandler:
|
||||||
|
TIM1_CC_IRQHandler:
|
||||||
|
TIM2_IRQHandler:
|
||||||
|
TIM3_IRQHandler:
|
||||||
|
TIM4_IRQHandler:
|
||||||
|
I2C1_EV_IRQHandler:
|
||||||
|
I2C1_ER_IRQHandler:
|
||||||
|
I2C2_EV_IRQHandler:
|
||||||
|
I2C2_ER_IRQHandler:
|
||||||
|
SPI1_IRQHandler:
|
||||||
|
SPI2_IRQHandler:
|
||||||
|
USART1_IRQHandler:
|
||||||
|
USART2_IRQHandler:
|
||||||
|
USART3_IRQHandler:
|
||||||
|
EXTI15_10_IRQHandler:
|
||||||
|
RTCAlarm_IRQHandler:
|
||||||
|
USBWakeUp_IRQHandler:
|
||||||
|
TIM8_BRK_IRQHandler:
|
||||||
|
TIM8_UP_IRQHandler:
|
||||||
|
TIM8_TRG_COM_IRQHandler:
|
||||||
|
TIM8_CC_IRQHandler:
|
||||||
|
RNG_IRQHandler:
|
||||||
|
SDIO_IRQHandler:
|
||||||
|
TIM5_IRQHandler:
|
||||||
|
SPI3_IRQHandler:
|
||||||
|
UART4_IRQHandler:
|
||||||
|
UART5_IRQHandler:
|
||||||
|
TIM6_IRQHandler:
|
||||||
|
TIM7_IRQHandler:
|
||||||
|
DMA2_Channel1_IRQHandler:
|
||||||
|
DMA2_Channel2_IRQHandler:
|
||||||
|
DMA2_Channel3_IRQHandler:
|
||||||
|
DMA2_Channel4_IRQHandler:
|
||||||
|
DMA2_Channel5_IRQHandler:
|
||||||
|
ETH_IRQHandler:
|
||||||
|
ETH_WKUP_IRQHandler:
|
||||||
|
CAN2_TX_IRQHandler:
|
||||||
|
CAN2_RX0_IRQHandler:
|
||||||
|
CAN2_RX1_IRQHandler:
|
||||||
|
CAN2_SCE_IRQHandler:
|
||||||
|
USBFS_IRQHandler:
|
||||||
|
USBHSWakeup_IRQHandler:
|
||||||
|
USBHS_IRQHandler:
|
||||||
|
DVP_IRQHandler:
|
||||||
|
UART6_IRQHandler:
|
||||||
|
UART7_IRQHandler:
|
||||||
|
UART8_IRQHandler:
|
||||||
|
TIM9_BRK_IRQHandler:
|
||||||
|
TIM9_UP_IRQHandler:
|
||||||
|
TIM9_TRG_COM_IRQHandler:
|
||||||
|
TIM9_CC_IRQHandler:
|
||||||
|
TIM10_BRK_IRQHandler:
|
||||||
|
TIM10_UP_IRQHandler:
|
||||||
|
TIM10_TRG_COM_IRQHandler:
|
||||||
|
TIM10_CC_IRQHandler:
|
||||||
|
DMA2_Channel6_IRQHandler:
|
||||||
|
DMA2_Channel7_IRQHandler:
|
||||||
|
DMA2_Channel8_IRQHandler:
|
||||||
|
DMA2_Channel9_IRQHandler:
|
||||||
|
DMA2_Channel10_IRQHandler:
|
||||||
|
DMA2_Channel11_IRQHandler:
|
||||||
|
1:
|
||||||
|
j 1b
|
||||||
|
|
||||||
|
.section .text.handle_reset,"ax",@progbits
|
||||||
|
.weak handle_reset
|
||||||
|
.align 1
|
||||||
|
handle_reset:
|
||||||
|
.option push
|
||||||
|
.option norelax
|
||||||
|
la gp, __global_pointer$
|
||||||
|
.option pop
|
||||||
|
|
||||||
|
la sp, _eusrstack
|
||||||
|
|
||||||
|
/* Load data section from flash to RAM */
|
||||||
|
la a0, _data_lma
|
||||||
|
la a1, _data_vma
|
||||||
|
la a2, _edata
|
||||||
|
bgeu a1, a2, 2f
|
||||||
|
1:
|
||||||
|
lw t0, (a0)
|
||||||
|
sw t0, (a1)
|
||||||
|
addi a0, a0, 4
|
||||||
|
addi a1, a1, 4
|
||||||
|
bltu a1, a2, 1b
|
||||||
|
2:
|
||||||
|
/* Clear bss section */
|
||||||
|
la a0, _sbss
|
||||||
|
la a1, _ebss
|
||||||
|
bgeu a0, a1, 2f
|
||||||
|
1:
|
||||||
|
sw zero, (a0)
|
||||||
|
addi a0, a0, 4
|
||||||
|
bltu a0, a1, 1b
|
||||||
|
2:
|
||||||
|
/* Configure pipelining and instruction prediction */
|
||||||
|
li t0, 0x1f
|
||||||
|
csrw 0xbc0, t0
|
||||||
|
/* Enable interrupt nesting and hardware stack */
|
||||||
|
li t0, 0x0b
|
||||||
|
csrw 0x804, t0
|
||||||
|
/* Enable floating point and global interrupt, configure privileged mode */
|
||||||
|
li t0, 0x6088
|
||||||
|
csrw mstatus, t0
|
||||||
|
/* Configure the interrupt vector table recognition mode and entry address mode */
|
||||||
|
la t0, _vector_base
|
||||||
|
ori t0, t0, 3
|
||||||
|
csrw mtvec, t0
|
||||||
|
|
||||||
|
jal SystemInit
|
||||||
|
la t0, main
|
||||||
|
csrw mepc, t0
|
||||||
|
mret
|
||||||
|
|
||||||
|
|
||||||
Binary file not shown.
@@ -0,0 +1,47 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_conf.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : Library configuration file.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_CONF_H
|
||||||
|
#define __CH32V30x_CONF_H
|
||||||
|
|
||||||
|
#include <ch32v30x_it.h>
|
||||||
|
#include "ch32v30x_adc.h"
|
||||||
|
#include "ch32v30x_bkp.h"
|
||||||
|
#include "ch32v30x_can.h"
|
||||||
|
#include "ch32v30x_crc.h"
|
||||||
|
#include "ch32v30x_dac.h"
|
||||||
|
#include "ch32v30x_dbgmcu.h"
|
||||||
|
#include "ch32v30x_dma.h"
|
||||||
|
#include "ch32v30x_exti.h"
|
||||||
|
#include "ch32v30x_flash.h"
|
||||||
|
#include "ch32v30x_fsmc.h"
|
||||||
|
#include "ch32v30x_gpio.h"
|
||||||
|
#include "ch32v30x_i2c.h"
|
||||||
|
#include "ch32v30x_iwdg.h"
|
||||||
|
#include "ch32v30x_pwr.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
#include "ch32v30x_rtc.h"
|
||||||
|
#include "ch32v30x_sdio.h"
|
||||||
|
#include "ch32v30x_spi.h"
|
||||||
|
#include "ch32v30x_tim.h"
|
||||||
|
#include "ch32v30x_usart.h"
|
||||||
|
#include "ch32v30x_wwdg.h"
|
||||||
|
#include "ch32v30x_misc.h"
|
||||||
|
#include "ch32v30x_eth.h"
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CH32V30x_CONF_H */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,96 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_it.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2022/01/18
|
||||||
|
* Description : Main Interrupt Service Routines.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "eth_driver.h"
|
||||||
|
#include "ch32v30x_it.h"
|
||||||
|
|
||||||
|
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||||
|
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||||
|
void ETH_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||||
|
void TIM2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||||
|
void EXTI9_5_IRQHandler(void) __attribute__((interrupt()));
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* 毫秒计数器：由 TIM2_IRQHandler 每 WCHNETTIMERPERIOD ms 累加一次。
|
||||||
|
* main.c 通过 extern 声明后直接使用，无需 SysTick_Init()。
|
||||||
|
*********************************************************************/
|
||||||
|
volatile uint32_t sys_tick_ms = 0;
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NMI_Handler
|
||||||
|
*
|
||||||
|
* @brief This function handles NMI exception.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void NMI_Handler(void)
|
||||||
|
{
|
||||||
|
while (1)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn HardFault_Handler
|
||||||
|
*
|
||||||
|
* @brief This function handles Hard Fault exception.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void HardFault_Handler(void)
|
||||||
|
{
|
||||||
|
printf("HardFault_Handler\r\n");
|
||||||
|
printf("mepc :%08x\r\n", __get_MEPC());
|
||||||
|
printf("mcause:%08x\r\n", __get_MCAUSE());
|
||||||
|
printf("mtval :%08x\r\n", __get_MTVAL());
|
||||||
|
NVIC_SystemReset();
|
||||||
|
while(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI9_5_IRQHandler
|
||||||
|
*
|
||||||
|
* @brief This function handles GPIO exception.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void EXTI9_5_IRQHandler(void)
|
||||||
|
{
|
||||||
|
ETH_PHYLink( );
|
||||||
|
EXTI_ClearITPendingBit(EXTI_Line7); /* Clear Flag */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn ETH_IRQHandler
|
||||||
|
*
|
||||||
|
* @brief This function handles ETH exception.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void ETH_IRQHandler(void)
|
||||||
|
{
|
||||||
|
WCHNET_ETHIsr();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn TIM2_IRQHandler
|
||||||
|
*
|
||||||
|
* @brief This function handles TIM2 exception.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void TIM2_IRQHandler(void)
|
||||||
|
{
|
||||||
|
sys_tick_ms += WCHNETTIMERPERIOD; /* 累加实际间隔毫秒数 */
|
||||||
|
WCHNET_TimeIsr(WCHNETTIMERPERIOD);
|
||||||
|
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
|
||||||
|
}
|
||||||
|
|
||||||
@@ -0,0 +1,20 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_it.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains the headers of the interrupt handlers.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_IT_H
|
||||||
|
#define __CH32V30x_IT_H
|
||||||
|
|
||||||
|
#include "debug.h"
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CH32V30x_IT_H */
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,168 @@
|
|||||||
|
#include "ch32v30x.h"
|
||||||
|
#include "string.h"
|
||||||
|
#include "eth_driver.h"
|
||||||
|
#include "dvp.h"
|
||||||
|
|
||||||
|
#define KEEPALIVE_ENABLE 1
|
||||||
|
|
||||||
|
u8 MACAddr[6];
|
||||||
|
u8 IPAddr[4] = {192, 168, 1, 10};
|
||||||
|
u8 GWIPAddr[4] = {192, 168, 1, 1};
|
||||||
|
u8 IPMask[4] = {255, 255, 255, 0};
|
||||||
|
u8 DESIP[4] = {192, 168, 1, 50};
|
||||||
|
u16 desport = 5512;
|
||||||
|
u16 srcport = 5511;
|
||||||
|
|
||||||
|
u8 SocketId;
|
||||||
|
u8 socket[WCHNET_MAX_SOCKET_NUM];
|
||||||
|
u8 SocketRecvBuf[WCHNET_MAX_SOCKET_NUM][RECE_BUF_LEN];
|
||||||
|
|
||||||
|
void mStopIfError(u8 iError)
|
||||||
|
{
|
||||||
|
if (iError == WCHNET_ERR_SUCCESS) return;
|
||||||
|
printf("Error: %02X\r\n", (u16)iError);
|
||||||
|
}
|
||||||
|
|
||||||
|
void TIM2_Init(void)
|
||||||
|
{
|
||||||
|
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure = {0};
|
||||||
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
|
||||||
|
TIM_TimeBaseStructure.TIM_Period = WCHNETTIMERPERIOD * 1000 - 1;
|
||||||
|
TIM_TimeBaseStructure.TIM_Prescaler = SystemCoreClock / 1000000 - 1;
|
||||||
|
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
|
||||||
|
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
||||||
|
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
|
||||||
|
TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
|
||||||
|
TIM_Cmd(TIM2, ENABLE);
|
||||||
|
TIM_ClearITPendingBit(TIM2, TIM_IT_Update);
|
||||||
|
NVIC_EnableIRQ(TIM2_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
void WCHNET_CreateTcpSocket(void)
|
||||||
|
{
|
||||||
|
u8 i;
|
||||||
|
SOCK_INF TmpSocketInf;
|
||||||
|
memset((void *)&TmpSocketInf, 0, sizeof(SOCK_INF));
|
||||||
|
memcpy((void *)TmpSocketInf.IPAddr, DESIP, 4);
|
||||||
|
TmpSocketInf.DesPort = desport;
|
||||||
|
TmpSocketInf.SourPort = srcport++;
|
||||||
|
TmpSocketInf.ProtoType = PROTO_TYPE_TCP;
|
||||||
|
TmpSocketInf.RecvBufLen = RECE_BUF_LEN;
|
||||||
|
i = WCHNET_SocketCreat(&SocketId, &TmpSocketInf);
|
||||||
|
printf("SocketId %d\r\n", SocketId);
|
||||||
|
mStopIfError(i);
|
||||||
|
i = WCHNET_SocketConnect(SocketId);
|
||||||
|
mStopIfError(i);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* PC -> MCU 收到数据后回环，同时可在此处理PC下发的指令 */
|
||||||
|
void WCHNET_DataLoopback(u8 id)
|
||||||
|
{
|
||||||
|
u32 len;
|
||||||
|
u32 endAddr = SocketInf[id].RecvStartPoint + SocketInf[id].RecvBufLen;
|
||||||
|
|
||||||
|
if ((SocketInf[id].RecvReadPoint + SocketInf[id].RecvRemLen) > endAddr)
|
||||||
|
len = endAddr - SocketInf[id].RecvReadPoint;
|
||||||
|
else
|
||||||
|
len = SocketInf[id].RecvRemLen;
|
||||||
|
|
||||||
|
if (WCHNET_SocketSend(id, (u8 *)SocketInf[id].RecvReadPoint, &len) == WCHNET_ERR_SUCCESS)
|
||||||
|
WCHNET_SocketRecv(id, NULL, &len);
|
||||||
|
}
|
||||||
|
|
||||||
|
void WCHNET_HandleSockInt(u8 socketid, u8 intstat)
|
||||||
|
{
|
||||||
|
u8 i;
|
||||||
|
|
||||||
|
if (intstat & SINT_STAT_RECV)
|
||||||
|
{
|
||||||
|
WCHNET_DataLoopback(socketid);
|
||||||
|
}
|
||||||
|
if (intstat & SINT_STAT_CONNECT)
|
||||||
|
{
|
||||||
|
#if KEEPALIVE_ENABLE
|
||||||
|
WCHNET_SocketSetKeepLive(socketid, ENABLE);
|
||||||
|
#endif
|
||||||
|
WCHNET_ModifyRecvBuf(socketid, (u32)SocketRecvBuf[socketid], RECE_BUF_LEN);
|
||||||
|
for (i = 0; i < WCHNET_MAX_SOCKET_NUM; i++) {
|
||||||
|
if (socket[i] == 0xff) { socket[i] = socketid; break; }
|
||||||
|
}
|
||||||
|
printf("TCP Connect Success, socket id: %d\r\n", socketid);
|
||||||
|
}
|
||||||
|
if (intstat & SINT_STAT_DISCONNECT)
|
||||||
|
{
|
||||||
|
for (i = 0; i < WCHNET_MAX_SOCKET_NUM; i++) {
|
||||||
|
if (socket[i] == socketid) { socket[i] = 0xff; break; }
|
||||||
|
}
|
||||||
|
printf("TCP Disconnect\r\n");
|
||||||
|
}
|
||||||
|
if (intstat & SINT_STAT_TIM_OUT)
|
||||||
|
{
|
||||||
|
for (i = 0; i < WCHNET_MAX_SOCKET_NUM; i++) {
|
||||||
|
if (socket[i] == socketid) { socket[i] = 0xff; break; }
|
||||||
|
}
|
||||||
|
printf("TCP Timeout\r\n");
|
||||||
|
WCHNET_CreateTcpSocket();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void WCHNET_HandleGlobalInt(void)
|
||||||
|
{
|
||||||
|
u8 intstat;
|
||||||
|
u16 i;
|
||||||
|
u8 socketint;
|
||||||
|
intstat = WCHNET_GetGlobalInt();
|
||||||
|
if (intstat & GINT_STAT_UNREACH) printf("GINT_STAT_UNREACH\r\n");
|
||||||
|
if (intstat & GINT_STAT_IP_CONFLI) printf("GINT_STAT_IP_CONFLI\r\n");
|
||||||
|
if (intstat & GINT_STAT_PHY_CHANGE) {
|
||||||
|
if (WCHNET_GetPHYStatus() & PHY_Linked_Status)
|
||||||
|
printf("PHY Link Success\r\n");
|
||||||
|
}
|
||||||
|
if (intstat & GINT_STAT_SOCKET) {
|
||||||
|
for (i = 0; i < WCHNET_MAX_SOCKET_NUM; i++) {
|
||||||
|
socketint = WCHNET_GetSocketInt(i);
|
||||||
|
if (socketint) WCHNET_HandleSockInt(i, socketint);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int main(void)
|
||||||
|
{
|
||||||
|
u8 i;
|
||||||
|
SystemCoreClockUpdate();
|
||||||
|
Delay_Init();
|
||||||
|
USART_Printf_Init(115200);
|
||||||
|
printf("TCPClient Test\r\nSystemClk:%d\r\n", SystemCoreClock);
|
||||||
|
printf("net version:%x\n", WCHNET_GetVer());
|
||||||
|
if (WCHNET_LIB_VER != WCHNET_GetVer()) printf("version error.\n");
|
||||||
|
|
||||||
|
WCHNET_GetMacAddr(MACAddr);
|
||||||
|
printf("mac addr:");
|
||||||
|
for (i = 0; i < 6; i++) printf("%x ", MACAddr[i]);
|
||||||
|
printf("\n");
|
||||||
|
|
||||||
|
DVP_Init();
|
||||||
|
TIM2_Init();
|
||||||
|
|
||||||
|
i = ETH_LibInit(IPAddr, GWIPAddr, IPMask, MACAddr);
|
||||||
|
mStopIfError(i);
|
||||||
|
if (i == WCHNET_ERR_SUCCESS) printf("WCHNET_LibInit Success\r\n");
|
||||||
|
|
||||||
|
#if KEEPALIVE_ENABLE
|
||||||
|
{
|
||||||
|
struct _KEEP_CFG cfg = {20000, 15000, 9};
|
||||||
|
WCHNET_ConfigKeepLive(&cfg);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
memset(socket, 0xff, WCHNET_MAX_SOCKET_NUM);
|
||||||
|
WCHNET_CreateTcpSocket();
|
||||||
|
|
||||||
|
while (1)
|
||||||
|
{
|
||||||
|
DVP_Task();
|
||||||
|
WCHNET_MainTask();
|
||||||
|
if (WCHNET_QueryGlobalInt())
|
||||||
|
WCHNET_HandleGlobalInt();
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,170 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : net_config.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.30
|
||||||
|
* Date : 2022/06/02
|
||||||
|
* Description : This file contains the configurations of
|
||||||
|
* Ethernet protocol stack library
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __NET_CONFIG_H__
|
||||||
|
#define __NET_CONFIG_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* socket configuration, IPRAW + UDP + TCP + TCP_LISTEN = number of sockets
|
||||||
|
*/
|
||||||
|
#define WCHNET_NUM_IPRAW 0 /* Number of IPRAW connections */
|
||||||
|
|
||||||
|
#define WCHNET_NUM_UDP 0 /* The number of UDP connections */
|
||||||
|
|
||||||
|
#define WCHNET_NUM_TCP 1 /* Number of TCP connections */
|
||||||
|
|
||||||
|
#define WCHNET_NUM_TCP_LISTEN 0 /* Number of TCP listening */
|
||||||
|
|
||||||
|
/* The number of sockets, the maximum is 31 */
|
||||||
|
#define WCHNET_MAX_SOCKET_NUM (WCHNET_NUM_IPRAW+WCHNET_NUM_UDP+WCHNET_NUM_TCP+WCHNET_NUM_TCP_LISTEN)
|
||||||
|
|
||||||
|
#define WCHNET_TCP_MSS 1460 /* Size of TCP MSS*/
|
||||||
|
|
||||||
|
#define WCHNET_NUM_POOL_BUF (WCHNET_NUM_TCP*2+2) /* The number of POOL BUFs, the number of receive queues */
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* MAC queue configuration
|
||||||
|
*/
|
||||||
|
#define ETH_TXBUFNB 2 /* The number of descriptors sent by the MAC */
|
||||||
|
|
||||||
|
#define ETH_RXBUFNB 7 /* Number of MAC received descriptors */
|
||||||
|
|
||||||
|
#ifndef ETH_MAX_PACKET_SIZE
|
||||||
|
#define ETH_RX_BUF_SZE 1520 /* MAC receive buffer length, an integer multiple of 4 */
|
||||||
|
#define ETH_TX_BUF_SZE 1520 /* MAC send buffer length, an integer multiple of 4 */
|
||||||
|
#else
|
||||||
|
#define ETH_RX_BUF_SZE ETH_MAX_PACKET_SIZE
|
||||||
|
#define ETH_TX_BUF_SZE ETH_MAX_PACKET_SIZE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* Functional configuration
|
||||||
|
*/
|
||||||
|
#define WCHNET_PING_ENABLE 1 /* PING is enabled, PING is enabled by default */
|
||||||
|
|
||||||
|
#define TCP_RETRY_COUNT 20 /* The number of TCP retransmissions, the default value is 20 */
|
||||||
|
|
||||||
|
#define TCP_RETRY_PERIOD 10 /* TCP retransmission period, the default value is 10, the unit is 50ms */
|
||||||
|
|
||||||
|
#define SOCKET_SEND_RETRY 0 /* Send failed retry configuration, 1: enable, 0: disable */
|
||||||
|
|
||||||
|
#define HARDWARE_CHECKSUM_CONFIG 0 /* Hardware checksum checking and insertion configuration, 1: enable, 0: disable */
|
||||||
|
|
||||||
|
#define FINE_DHCP_PERIOD 8 /* Fine DHCP period, the default value is 8, the unit is 250ms */
|
||||||
|
|
||||||
|
#define CFG0_TCP_SEND_COPY 1 /* TCP send buffer copy, 1: copy, 0: not copy */
|
||||||
|
|
||||||
|
#define CFG0_TCP_RECV_COPY 1 /* TCP receive replication optimization, internal debugging use */
|
||||||
|
|
||||||
|
#define CFG0_TCP_OLD_DELETE 0 /* Delete oldest TCP connection, 1: enable, 0: disable */
|
||||||
|
|
||||||
|
#define CFG0_IP_REASS_PBUFS 0 /* Number of reassembled IP PBUFs */
|
||||||
|
|
||||||
|
#define CFG0_TCP_DEALY_ACK_DISABLE 1 /* 1: disable TCP delay ACK 0: enable TCP delay ACK */
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* Memory related configuration
|
||||||
|
*/
|
||||||
|
/* If you want to achieve a higher transmission speed,
|
||||||
|
* try to increase RECE_BUF_LEN to (WCHNET_TCP_MSS*4)
|
||||||
|
* and increase WCHNET_NUM_TCP_SEG to (WCHNET_NUM_TCP*4)*/
|
||||||
|
#define RECE_BUF_LEN (WCHNET_TCP_MSS*2) /* socket receive buffer size */
|
||||||
|
|
||||||
|
#define WCHNET_NUM_PBUF WCHNET_NUM_POOL_BUF /* Number of PBUF structures */
|
||||||
|
|
||||||
|
#define WCHNET_NUM_TCP_SEG (WCHNET_NUM_TCP*2) /* The number of TCP segments used to send */
|
||||||
|
|
||||||
|
#define WCHNET_MEM_HEAP_SIZE (((WCHNET_TCP_MSS+0x10+54+8)*WCHNET_NUM_TCP_SEG)+ETH_TX_BUF_SZE+64+2*0x18) /* memory heap size */
|
||||||
|
|
||||||
|
#define WCHNET_NUM_ARP_TABLE 50 /* Number of ARP lists */
|
||||||
|
|
||||||
|
#define WCHNET_MEM_ALIGNMENT 4 /* 4 byte alignment */
|
||||||
|
|
||||||
|
#if CFG0_IP_REASS_PBUFS
|
||||||
|
#define WCHNET_NUM_IP_REASSDATA 2 /* Number of reassembled IP structures */
|
||||||
|
/*1: When using the fragmentation function,
|
||||||
|
* ensure that the size of WCHNET_SIZE_POOL_BUF is large enough to store a single fragmented packet*/
|
||||||
|
#define WCHNET_SIZE_POOL_BUF (((1500 + 14 + 4) + 3) & ~3) /* Buffer size for receiving a single packet */
|
||||||
|
/*2: When creating a socket that can receive fragmented packets,
|
||||||
|
* ensure that "RecvBufLen" member of the "struct _SOCK_INF" structure
|
||||||
|
* (the parameter initialized when calling WCHNET_SocketCreat) is sufficient
|
||||||
|
* to receive a complete fragmented packet */
|
||||||
|
#else
|
||||||
|
#define WCHNET_NUM_IP_REASSDATA 0 /* Number of reassembled IP structures */
|
||||||
|
#define WCHNET_SIZE_POOL_BUF (((WCHNET_TCP_MSS + 40 + 14 + 4) + 3) & ~3) /* Buffer size for receiving a single packet */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Check receive buffer */
|
||||||
|
#if(WCHNET_NUM_POOL_BUF * WCHNET_SIZE_POOL_BUF < ETH_RX_BUF_SZE)
|
||||||
|
#error "WCHNET_NUM_POOL_BUF or WCHNET_TCP_MSS Error"
|
||||||
|
#error "Please Increase WCHNET_NUM_POOL_BUF or WCHNET_TCP_MSS to make sure the receive buffer is sufficient"
|
||||||
|
#endif
|
||||||
|
/* Check the configuration of the SOCKET quantity */
|
||||||
|
#if( WCHNET_NUM_TCP_LISTEN && !WCHNET_NUM_TCP )
|
||||||
|
#error "WCHNET_NUM_TCP Error,Please Configure WCHNET_NUM_TCP >= 1"
|
||||||
|
#endif
|
||||||
|
/* Check byte alignment must be a multiple of 4 */
|
||||||
|
#if((WCHNET_MEM_ALIGNMENT % 4) || (WCHNET_MEM_ALIGNMENT == 0))
|
||||||
|
#error "WCHNET_MEM_ALIGNMENT Error,Please Configure WCHNET_MEM_ALIGNMENT = 4 * N, N >=1"
|
||||||
|
#endif
|
||||||
|
/* TCP maximum segment length */
|
||||||
|
#if((WCHNET_TCP_MSS > 1460) || (WCHNET_TCP_MSS < 60))
|
||||||
|
#error "WCHNET_TCP_MSS Error,Please Configure WCHNET_TCP_MSS >= 60 && WCHNET_TCP_MSS <= 1460"
|
||||||
|
#endif
|
||||||
|
/* Number of ARP cache tables */
|
||||||
|
#if((WCHNET_NUM_ARP_TABLE > 0X7F) || (WCHNET_NUM_ARP_TABLE < 1))
|
||||||
|
#error "WCHNET_NUM_ARP_TABLE Error,Please Configure WCHNET_NUM_ARP_TABLE >= 1 && WCHNET_NUM_ARP_TABLE <= 0X7F"
|
||||||
|
#endif
|
||||||
|
/* Check POOL BUF configuration */
|
||||||
|
#if(WCHNET_NUM_POOL_BUF < 1)
|
||||||
|
#error "WCHNET_NUM_POOL_BUF Error,Please Configure WCHNET_NUM_POOL_BUF >= 1"
|
||||||
|
#endif
|
||||||
|
/* Check PBUF structure configuration */
|
||||||
|
#if(WCHNET_NUM_PBUF < 1)
|
||||||
|
#error "WCHNET_NUM_PBUF Error,Please Configure WCHNET_NUM_PBUF >= 1"
|
||||||
|
#endif
|
||||||
|
/* Check IP Assignment Configuration */
|
||||||
|
#if(CFG0_IP_REASS_PBUFS && ((WCHNET_NUM_IP_REASSDATA > 10) || (WCHNET_NUM_IP_REASSDATA < 1)))
|
||||||
|
#error "WCHNET_NUM_IP_REASSDATA Error,Please Configure WCHNET_NUM_IP_REASSDATA < 10 && WCHNET_NUM_IP_REASSDATA >= 1 "
|
||||||
|
#endif
|
||||||
|
/* Check the number of reassembled IP PBUFs */
|
||||||
|
#if(CFG0_IP_REASS_PBUFS > WCHNET_NUM_POOL_BUF)
|
||||||
|
#error "WCHNET_NUM_POOL_BUF Error,Please Configure CFG0_IP_REASS_PBUFS < WCHNET_NUM_POOL_BUF"
|
||||||
|
#endif
|
||||||
|
/* Check Timer period, in Ms. */
|
||||||
|
#if(WCHNETTIMERPERIOD > 50)
|
||||||
|
#error "WCHNETTIMERPERIOD Error,Please Configure WCHNETTIMERPERIOD < 50"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configuration value 0 */
|
||||||
|
#define WCHNET_MISC_CONFIG0 (((CFG0_TCP_SEND_COPY) << 0) |\
|
||||||
|
((CFG0_TCP_RECV_COPY) << 1) |\
|
||||||
|
((CFG0_TCP_OLD_DELETE) << 2) |\
|
||||||
|
((CFG0_IP_REASS_PBUFS) << 3) |\
|
||||||
|
((CFG0_TCP_DEALY_ACK_DISABLE) << 8))
|
||||||
|
/* Configuration value 1 */
|
||||||
|
#define WCHNET_MISC_CONFIG1 (((WCHNET_MAX_SOCKET_NUM)<<0)|\
|
||||||
|
((WCHNET_PING_ENABLE) << 13) |\
|
||||||
|
((TCP_RETRY_COUNT) << 14) |\
|
||||||
|
((TCP_RETRY_PERIOD) << 19) |\
|
||||||
|
((SOCKET_SEND_RETRY) << 25) |\
|
||||||
|
((HARDWARE_CHECKSUM_CONFIG) << 26)|\
|
||||||
|
((FINE_DHCP_PERIOD) << 27))
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,32 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : system_ch32v30x.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : CH32V30x Device Peripheral Access Layer System Header File.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __SYSTEM_CH32V30x_H
|
||||||
|
#define __SYSTEM_CH32V30x_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||||
|
|
||||||
|
/* System_Exported_Functions */
|
||||||
|
extern void SystemInit(void);
|
||||||
|
extern void SystemCoreClockUpdate(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /*__CH32V30x_SYSTEM_H */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,21 @@
|
|||||||
|
################################################################################
|
||||||
|
# MRS Version: 1.9.0
|
||||||
|
# 自动生成的文件。不要编辑！
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
# Add inputs and outputs from these tool invocations to the build variables
|
||||||
|
C_SRCS += \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Core/core_riscv.c
|
||||||
|
|
||||||
|
OBJS += \
|
||||||
|
./Core/core_riscv.o
|
||||||
|
|
||||||
|
C_DEPS += \
|
||||||
|
./Core/core_riscv.d
|
||||||
|
|
||||||
|
|
||||||
|
# Each subdirectory must supply rules for building sources it contributes
|
||||||
|
Core/core_riscv.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Core/core_riscv.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
|
||||||
@@ -0,0 +1,27 @@
|
|||||||
|
################################################################################
|
||||||
|
# MRS Version: 1.9.0
|
||||||
|
# 自动生成的文件。不要编辑！
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
# Add inputs and outputs from these tool invocations to the build variables
|
||||||
|
C_SRCS += \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Debug/debug.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Debug/dvp.c
|
||||||
|
|
||||||
|
OBJS += \
|
||||||
|
./Debug/debug.o \
|
||||||
|
./Debug/dvp.o
|
||||||
|
|
||||||
|
C_DEPS += \
|
||||||
|
./Debug/debug.d \
|
||||||
|
./Debug/dvp.d
|
||||||
|
|
||||||
|
|
||||||
|
# Each subdirectory must supply rules for building sources it contributes
|
||||||
|
Debug/debug.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Debug/debug.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Debug/dvp.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Debug/dvp.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
|
||||||
@@ -0,0 +1,21 @@
|
|||||||
|
################################################################################
|
||||||
|
# MRS Version: 1.9.0
|
||||||
|
# 自动生成的文件。不要编辑！
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
# Add inputs and outputs from these tool invocations to the build variables
|
||||||
|
C_SRCS += \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/ETH/NetLib/eth_driver_RGMII.c
|
||||||
|
|
||||||
|
OBJS += \
|
||||||
|
./NetLib/eth_driver_RGMII.o
|
||||||
|
|
||||||
|
C_DEPS += \
|
||||||
|
./NetLib/eth_driver_RGMII.d
|
||||||
|
|
||||||
|
|
||||||
|
# Each subdirectory must supply rules for building sources it contributes
|
||||||
|
NetLib/eth_driver_RGMII.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/ETH/NetLib/eth_driver_RGMII.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
|
||||||
@@ -0,0 +1,171 @@
|
|||||||
|
################################################################################
|
||||||
|
# MRS Version: 1.9.0
|
||||||
|
# 自动生成的文件。不要编辑！
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
# Add inputs and outputs from these tool invocations to the build variables
|
||||||
|
C_SRCS += \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_adc.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_bkp.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_can.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_crc.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_dac.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_dbgmcu.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_dma.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_dvp.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_eth.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_exti.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_flash.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_fsmc.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_gpio.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_i2c.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_iwdg.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_misc.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_opa.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_pwr.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_rcc.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_rng.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_rtc.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_sdio.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_spi.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_tim.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_usart.c \
|
||||||
|
D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_wwdg.c
|
||||||
|
|
||||||
|
OBJS += \
|
||||||
|
./Peripheral/src/ch32v30x_adc.o \
|
||||||
|
./Peripheral/src/ch32v30x_bkp.o \
|
||||||
|
./Peripheral/src/ch32v30x_can.o \
|
||||||
|
./Peripheral/src/ch32v30x_crc.o \
|
||||||
|
./Peripheral/src/ch32v30x_dac.o \
|
||||||
|
./Peripheral/src/ch32v30x_dbgmcu.o \
|
||||||
|
./Peripheral/src/ch32v30x_dma.o \
|
||||||
|
./Peripheral/src/ch32v30x_dvp.o \
|
||||||
|
./Peripheral/src/ch32v30x_eth.o \
|
||||||
|
./Peripheral/src/ch32v30x_exti.o \
|
||||||
|
./Peripheral/src/ch32v30x_flash.o \
|
||||||
|
./Peripheral/src/ch32v30x_fsmc.o \
|
||||||
|
./Peripheral/src/ch32v30x_gpio.o \
|
||||||
|
./Peripheral/src/ch32v30x_i2c.o \
|
||||||
|
./Peripheral/src/ch32v30x_iwdg.o \
|
||||||
|
./Peripheral/src/ch32v30x_misc.o \
|
||||||
|
./Peripheral/src/ch32v30x_opa.o \
|
||||||
|
./Peripheral/src/ch32v30x_pwr.o \
|
||||||
|
./Peripheral/src/ch32v30x_rcc.o \
|
||||||
|
./Peripheral/src/ch32v30x_rng.o \
|
||||||
|
./Peripheral/src/ch32v30x_rtc.o \
|
||||||
|
./Peripheral/src/ch32v30x_sdio.o \
|
||||||
|
./Peripheral/src/ch32v30x_spi.o \
|
||||||
|
./Peripheral/src/ch32v30x_tim.o \
|
||||||
|
./Peripheral/src/ch32v30x_usart.o \
|
||||||
|
./Peripheral/src/ch32v30x_wwdg.o
|
||||||
|
|
||||||
|
C_DEPS += \
|
||||||
|
./Peripheral/src/ch32v30x_adc.d \
|
||||||
|
./Peripheral/src/ch32v30x_bkp.d \
|
||||||
|
./Peripheral/src/ch32v30x_can.d \
|
||||||
|
./Peripheral/src/ch32v30x_crc.d \
|
||||||
|
./Peripheral/src/ch32v30x_dac.d \
|
||||||
|
./Peripheral/src/ch32v30x_dbgmcu.d \
|
||||||
|
./Peripheral/src/ch32v30x_dma.d \
|
||||||
|
./Peripheral/src/ch32v30x_dvp.d \
|
||||||
|
./Peripheral/src/ch32v30x_eth.d \
|
||||||
|
./Peripheral/src/ch32v30x_exti.d \
|
||||||
|
./Peripheral/src/ch32v30x_flash.d \
|
||||||
|
./Peripheral/src/ch32v30x_fsmc.d \
|
||||||
|
./Peripheral/src/ch32v30x_gpio.d \
|
||||||
|
./Peripheral/src/ch32v30x_i2c.d \
|
||||||
|
./Peripheral/src/ch32v30x_iwdg.d \
|
||||||
|
./Peripheral/src/ch32v30x_misc.d \
|
||||||
|
./Peripheral/src/ch32v30x_opa.d \
|
||||||
|
./Peripheral/src/ch32v30x_pwr.d \
|
||||||
|
./Peripheral/src/ch32v30x_rcc.d \
|
||||||
|
./Peripheral/src/ch32v30x_rng.d \
|
||||||
|
./Peripheral/src/ch32v30x_rtc.d \
|
||||||
|
./Peripheral/src/ch32v30x_sdio.d \
|
||||||
|
./Peripheral/src/ch32v30x_spi.d \
|
||||||
|
./Peripheral/src/ch32v30x_tim.d \
|
||||||
|
./Peripheral/src/ch32v30x_usart.d \
|
||||||
|
./Peripheral/src/ch32v30x_wwdg.d
|
||||||
|
|
||||||
|
|
||||||
|
# Each subdirectory must supply rules for building sources it contributes
|
||||||
|
Peripheral/src/ch32v30x_adc.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_adc.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_bkp.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_bkp.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_can.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_can.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_crc.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_crc.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_dac.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_dac.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_dbgmcu.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_dbgmcu.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_dma.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_dma.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_dvp.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_dvp.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_eth.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_eth.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_exti.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_exti.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_flash.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_flash.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_fsmc.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_fsmc.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_gpio.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_gpio.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_i2c.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_i2c.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_iwdg.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_iwdg.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_misc.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_misc.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_opa.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_opa.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_pwr.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_pwr.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_rcc.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_rcc.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_rng.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_rng.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_rtc.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_rtc.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_sdio.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_sdio.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_spi.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_spi.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_tim.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_tim.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_usart.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_usart.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
Peripheral/src/ch32v30x_wwdg.o: D:/Project/MINI212/ALL/soft/CH32V307EVT/EVT/EXAM/SRC/Peripheral/src/ch32v30x_wwdg.c
|
||||||
|
@ @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\NetLib" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Core" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Debug" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\SRC\Peripheral\inc" -I"D:\Project\MINI212\ALL\soft\CH32V307EVT\EVT\EXAM\ETH\TCPClient\User" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<"
|
||||||
|
@ @
|
||||||
|
|
||||||
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Reference in New Issue
Block a user