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/*
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* FreeRTOS Kernel V10.4.6
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
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*
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* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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*
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* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* !!!NOTE!!!
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* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
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* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
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* compiler's!) include path. For example, if the chip in use includes a core
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* local interrupter (CLINT) and does not include any chip specific register
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* extensions then add the path below to the assembler's include path:
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
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*
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*/
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHAS_SIFIVE_CLINT 0
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#define portasmHAS_MTIME 0
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/* if you want to use FPU, please define ARCH_FPU and enable float point and ABI of gcc */
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#define ARCH_FPU 0
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#if ARCH_FPU
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#define portasmADDITIONAL_CONTEXT_SIZE 32 /* Must be even number on 32-bit cores. */
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE* portWORD_SIZE)
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fsw f0, 1*portWORD_SIZE(sp)
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fsw f1, 2*portWORD_SIZE(sp)
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fsw f2, 3*portWORD_SIZE(sp)
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fsw f3, 4*portWORD_SIZE(sp)
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fsw f4, 5*portWORD_SIZE(sp)
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fsw f5, 6*portWORD_SIZE(sp)
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fsw f6, 7*portWORD_SIZE(sp)
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fsw f7, 8*portWORD_SIZE(sp)
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fsw f8, 9*portWORD_SIZE(sp)
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fsw f9, 10*portWORD_SIZE(sp)
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fsw f10, 11*portWORD_SIZE(sp)
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fsw f11, 12*portWORD_SIZE(sp)
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fsw f12, 13*portWORD_SIZE(sp)
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fsw f13, 14*portWORD_SIZE(sp)
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fsw f14, 15*portWORD_SIZE(sp)
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fsw f15, 16*portWORD_SIZE(sp)
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fsw f16, 17*portWORD_SIZE(sp)
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fsw f17, 18*portWORD_SIZE(sp)
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fsw f18, 19*portWORD_SIZE(sp)
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fsw f19, 20*portWORD_SIZE(sp)
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fsw f20, 21*portWORD_SIZE(sp)
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fsw f21, 22*portWORD_SIZE(sp)
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fsw f22, 23*portWORD_SIZE(sp)
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fsw f23, 24*portWORD_SIZE(sp)
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fsw f24, 25*portWORD_SIZE(sp)
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fsw f25, 26*portWORD_SIZE(sp)
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fsw f26, 27*portWORD_SIZE(sp)
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fsw f27, 28*portWORD_SIZE(sp)
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fsw f28, 29*portWORD_SIZE(sp)
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fsw f29, 30*portWORD_SIZE(sp)
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fsw f30, 31*portWORD_SIZE(sp)
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fsw f31, 32*portWORD_SIZE(sp)
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.endm
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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flw f0, 1*portWORD_SIZE(sp)
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flw f1, 2*portWORD_SIZE(sp)
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flw f2, 3*portWORD_SIZE(sp)
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flw f3, 4*portWORD_SIZE(sp)
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flw f4, 5*portWORD_SIZE(sp)
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flw f5, 6*portWORD_SIZE(sp)
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flw f6, 7*portWORD_SIZE(sp)
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flw f7, 8*portWORD_SIZE(sp)
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flw f8, 9*portWORD_SIZE(sp)
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flw f9, 10*portWORD_SIZE(sp)
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flw f10, 11*portWORD_SIZE(sp)
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flw f11, 12*portWORD_SIZE(sp)
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flw f12, 13*portWORD_SIZE(sp)
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flw f13, 14*portWORD_SIZE(sp)
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flw f14, 15*portWORD_SIZE(sp)
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flw f15, 16*portWORD_SIZE(sp)
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flw f16, 17*portWORD_SIZE(sp)
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flw f17, 18*portWORD_SIZE(sp)
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flw f18, 19*portWORD_SIZE(sp)
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flw f19, 20*portWORD_SIZE(sp)
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flw f20, 21*portWORD_SIZE(sp)
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flw f21, 22*portWORD_SIZE(sp)
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flw f22, 23*portWORD_SIZE(sp)
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flw f23, 24*portWORD_SIZE(sp)
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flw f24, 25*portWORD_SIZE(sp)
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flw f25, 26*portWORD_SIZE(sp)
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flw f26, 27*portWORD_SIZE(sp)
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flw f27, 28*portWORD_SIZE(sp)
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flw f28, 29*portWORD_SIZE(sp)
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flw f29, 30*portWORD_SIZE(sp)
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flw f30, 31*portWORD_SIZE(sp)
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flw f31, 32*portWORD_SIZE(sp)
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addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE* portWORD_SIZE)
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.endm
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#else
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#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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/* No additional registers to save, so this macro does nothing. */
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.endm
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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/* No additional registers to restore, so this macro does nothing. */
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.endm
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#endif
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@@ -0,0 +1,23 @@
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
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*
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* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
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* is common to all currently supported RISC-V chips. There is only one
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* portASM.S file because the same file is built for all RISC-V target chips.
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*
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* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
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* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
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* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
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* as there are multiple RISC-V chip implementations.
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*
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* !!!NOTE!!!
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* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
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* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
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* compiler's!) include path. For example, if the chip in use includes a core
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* local interrupter (CLINT) and does not include any chip specific register
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* extensions then add the path below to the assembler's include path:
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
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*
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*/
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